Other Parts Discussed in Thread: SN74LVC1G97
Team,
My customer has the following question:
Could you help us out with some basic understanding of how TI defines propagation delay (t_pd). We have a design using multiple SN74LVC1G97/98 configurable gates. We want to calculate our nominal propagation delay through these but the datasheet shows a wide range (1.1 - 6.1 ns for 5V). In our case we aren't driving a large load, just another logic gate. Can any guidance be provided on what a better estimate would be? How much of the delay is internal and how much is due to the load, Maybe a rough equation t_pd = ??ns + c_l * ??ns?
Regards
Aaron