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SN74AUP1G06: Feeding inverter VCC from logic to minimise quiescent drain

Edward Matos
Intellectual 330 points
Part Number: SN74AUP1G06
Other Parts Discussed in Thread: SN74AUP1G14, TINA-TI

Hello,

The reset pin of my MCU is pulled high (3.3V) during normal operation. My system has a single connector and I must use this connector both in normal use, and for interfacing with a programming tool in the factory.

The reset pin is broken out to this multi-purpose connector as it is needed for firmware flashing. It is not used in normal use. However, the connector interface itself has a requirement that means this pin shall never assert more than 1V during normal use.

Therefore I have added an inverter, so that this logic level becomes normally low at the connector side. During normal use the voltage level at the connector is now high-z (allowing the voltage level at the MCU to be pulled HIGH), and during factory firmware flashing the voltage level at the connector is be pulled up to 3.3V (resulting in a LOW reset pulse at the MCU).

Furthermore the application requires an exceedingly low quiscent current drain during normal use. After a brief search, the SN74AUP1G06 seems like a reasonable choice.

I was thinking that a nice way of minimising the quiescent current drain of this device would be to power this inverter from the reset pulse itself. Therefore during normal use VCC is high-z, and the quiescent current drain is limited to the "Ioff" flow through the output pin to ground. During programming the 3.3V reset pulse also powers the inverter for the short period it is needed.

Would this work? Some concerns I could imagine are:

  1. The programming pulse must obviously be able to drive a few mA to power the inverter, this might result in a fairly slow switch on - potentially leading to undefined transient behaviour?
  2. I should probably take care to ensure a low resistance path between VCC and the inverter input, to avoid a transient period during power up where VCC is lower than the input.
  3. To minimise "Ioff" would it be better to leave VCC as high-Z? Or use a 10K pull-down to ground?

Finally, part availability is needed until 2030. I note that the datasheet has the year 2004 in the copyright. Therefore, any suggestions for alternative parts recommended for new designs would be very welcome if there are concerns about this part selection due to likely long-term availability, or other.

Many thanks in advance for any help offered.

Best regards,

Edward

  • 0
    TI__Genius 16725 points

    Hi Edward,

    I think you have captured all the concerns I would have with powering the inverter with an I/O on your MCU.

    1. When the inverter inputs transition states, there is a large current draw (some mA) that can occur and will cause your VCC to be shorted to GND for a very short period of time. Now if your VCC does not have the current sourcing ability, it will not let the inputs transition from a low to a high and there will be large oscillations on your input.

    2. For this device, the inputs can be greater than VCC. The concern is that the transition rate of your input would need to be very fast. The datasheet requires faster than 200ns/V.

    3. I would recommend pulling down Vcc to GND since leaving it HIGH-Z may cause currents greater than Ioff to flow.

    There is no need to worry about this part life being ended.

    TI makes an effort to not obsolete products out of convenience. Convenience means a low running device, poor yields, limited customer adoption or similar items. TI’s obsolescence withdrawal schedule provides a longer lead time than the industry standard. TI allows 12 months for the last order and an additional six months to take final delivery of obsolete items.

    Thanks!

    -Karan

  • 0 in reply to Karan Kotadia
    Intellectual 330 points

    Hi Karan,

    Thanks a lot for the fast and comprehensive reply. There are two solutions I would propose to mitigate the risks we have discussed and I'd be very grateful for your thoughts on them:

    1. Instead of using the open-drain variant of this device I initially proposed (SN74AUP1G06), how about I use the Schmitt Trigger (push-pull) variant? (SN74AUP1G14) This would presumably eliminate the risk of oscillations on the output?
    2. To my best understanding the Schmitt Trigger will not result in a lower supply current (indeed, it may even be higher). However, I have just remembered that I will also need to add an inverter to the reset signal of the 3rd party programming tool. So the line driving both the VCC and the input signal at the inverter on the device-side would not be driven by a programmer pin, but by the output of another inverter. Therefore, presumably the inverter on the device-side could be trusted to power-up relatively quickly? I have drawn up the circuit diagram below to assist with communication.

    Does this seem safe? The 3.3V supply would low-impedance with added capacitance.

    I would propose using the same Schmitt-trigger inverter in both places.

    Many thanks in advance for your thoughts on the matter.

    Best regards,

    Edward

  • 0 in reply to Edward Matos
    TI__Genius 16725 points

    Hi Edward

    This solution will not work. It doesn't matter if the device is push pull or open drain. The input structure is always the same as shown in the FAQ I had previously linked.

    When the input is transitioning states, the supply gets shorted to GND through about 50 Ohm resistance. Your supply needs to be strong enough to handle this much current draw. The output driver will not be able to handle this much current and mostly likely will be damaged.

    Here is a tina circuit I created to test this.

    7776.E2EQuestion.TSC

    Thanks!

    -Karan

  • 0 in reply to Karan Kotadia
    Intellectual 330 points

    Hi Karan,

    Sorry for the late reply. Your post made me realise this would require some more in-depth work to analyse and therefore I decided to postpone it at the time. I have come back to it now. Unfortunately I initially couldn't get the TINA-TI model to work properly, but then noticed that the VCC and GND pins were flipped on the inverter. I have attached a version where this is corrected. I also changed the voltage generator waveform to a unit step, as the square wave was causing some kind of convergence problems. Finally, I added a current meter to try and capture the short you mention.

    /cfs-file/__key/communityserver-discussions-components-files/151/7776.E2EQuestion_5F00_EM.TSC

    The result seems to show exactly what you write. A high current is observed and the MCU voltage fails to rise. Shame. Probably best accept the quiescent current penalty then!

    Many thanks anyway for your help.

    Best regards,

    Edward