SN74LVC8T245-EP: Logic Buffers to weak for Termination Resistors

In http://www.ti.com/lit/ug/scba010/scba010.pdf it is stated that for Thevenin Termination
"proper drive currents must be maintained.". Which driver should I use then? An OPAMP?

Ok. Thanks for the answer!!

To sum it up you suggest me to "use a damping resistor at the input to match the input as much as possible to the transmission line".

So that means Thevenin Termination is not possible for 50 Ohm or even 120 Ohm Impedance with this kind of logic ICs.

Is there another Driver IC or OPAMP that would be recommended for driving a properly terminated Transmission line with a 150MHz 3,3V Signal?
This way I might also include more than one load IC per Signal. Eg. spread one Clock Signal to 5 IC's using one Driver…

Best regards,

Marco

Hey Marco,

Why are you dead set on terminating your transmission line for a digital logic signal? You're going to burn a lot of excess power just for a cleaner looking signal that ends up at half the input voltage anyways (unless this is what you want?).

In the vast majority of systems, there's no need for any type of termination for digital signals - just connection the buffer via a trace to the digital input.  In your system, you have exceptionally long lines that will produce a lot of ringing, so I would break the line up into smaller sections.

First, I have to assume that the signal coming in from the cable at 150 MHz is reaching Vt+(max)/Vt-(min) for the buffer I've selected. (ie the signal is of good integrity)

Place a 3.3V buffer capable of 300 Mbps operation (SN74AUP1G17) as close to the connection point of the cable as possible. The AUP family generally has a very smooth output transition and thus less issues with ringing, but you can add a series resistor at the buffer's output just to tune this a bit if you run into problems. 22 to 33 ohms is the most common value for these resistors.

* There aren't a lot of buffers that work well beyond 100 MHz for single-ended signals -- the fastest we have is the SN74AUC1G17, but it only works up to 2.7V and is really optimized for 1.8V operation. You could terminate the incoming signal at the input of your board to get ~1.8V and send the signal at that voltage instead, then convert at the distant end using a voltage translator such as SN74AXC1T45... but since I don't know if that will work, I'll continue on.

Limit unbuffered trace lengths to ~10-20 cm to reduce transmission line effects - add buffers every 10-20 cm.

The LVC family Dylan recommended is actually has extremely strong output drivers -- which is generally a good thing for fast signals, but with long traces I have found that the output signal can get pretty ugly past 100 MHz.

Dear Emrys,

thanks a lot for the detailed answer which helped me a lot.

Indeed I don't care about excess power or cost. For my test System I would like to have
more or less reliable and clean Signals to be able to analyse rise times, jitter etc.

I will follow your advice and use short trace lengths + small series termination resistors.

As an alternative to putting a Buffer every ~10cm I'm currently considering to use a M-LVDS System
for the Long PCB distance. Reading your AN-1926 This should work even if I use like 8 loads (Receivers) 
in parallel / on one bus (up to 125MHz). From reading this System looks relatively simple and reliable.
Or do you have any concerns about this? :)

Best regards,
Marco