SN74HC595B: serial to parallel conversion

The logic diagram shows that all eight shift register flip-flops share the same clock signal, and that the output of each flip-flop connects to the data input of the next flip-flop in the chain. (Whether this is a single Data input or separate Set/Reset inputs does not matter.)

To cascade multiple devices, do the same: route the same clock signal to all SRCLK inputs, and connect the output of the last shift register flip-flop (Q_H') in each device to the data input of the first flip-flop (SER) in the next device.

Typically, you would also want to share the SRCLR and RCLK signals.