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TXS0101: TXS0101 : I/O level interpretation and pull-up impact in HiZ status

Part Number: TXS0101

Dear E2E support, 
I contact to you about the component : the level shifter TXS0101. 
I read the TI documents about this component:
_ The application report: A guide to voltage translation with TXS-type translators,
_ Datasheet. 
I also went to the forum e2e. 
But I have always some questions about the compatibility of this component with my design. 
This component looks very flexible (push-pull, open-drain application) and very interesting for its performances. 
I don't have lots of experience in this kind of component. Perhaps I do some wrong interpretations or I have chosen a component not adapted to my design. 
Question 1
In the documents it is mentioned that the component has internal pull-up of 10k and when the OE pin is low, the I/O are in high impedance. 
On the diagram inside the datasheet, it seems that the pull-ups are always connected. 
Q: Can you confirm to me that when EO is low there is no connection between the I/O and the internal pull-ups ? 
Question 2
In my application I want to translate a voltage level of 1.8V to 3.3V and 3.3V to 1.8V (in function of the communication direction). 
Datarate max is 1Mps and it can be reduced.
After some checking on the high and low level of the different components I have some doubt about the compatibility in my case. 
Hereunder my analysis:
image.png
Before searching for another reference I want to be sure of my interpretation of the datasheet of the TXS0101 or the risk that I take if I use it or the confirmation that it can finally be used without restriction. 
 
In the datasheet of the TXS0101 we have:
image.png
I found the level really high or low compared to my other components that is really constraining for me. 
Output level:
That I don't understand is: Normally with the TXS0101 architecture when a high level is detected on an input the opposite output is really close to the Vcca or Vccb with the pull-up or directly linked to the Vcca and Vccb briefly with the one shot accelerator.  
Q: Why the Vcca or the Vccb are a factor of 0,67V for the min value of Voh ? 
Input level:
I found that the margin to detect a high or low level on the input is really low. 
I thought that the input will be larger, 
Q: how are they defined ? 
In my understanding it is linked to the Vgs voltage of the internal FET.  And I think I can have more margin on the input value if I take in account the evolution of the voltages around the FET with the voltage level of my application.
I didn't find information on the Vt voltage to take in account in the datasheet and same remark for the Vgsth of the FET. 
Q: Do you have this kind of information ? 
Or perhaps can I deduce this information with other datas in the datasheet ? 
If my reflexion is wrong can you explain to me the reason please ? 
Final questions:
Q: Do you think this component can be a good choice ? 
Q: What is the risk to use this component in my case if the voltage levels are not really respected ? 
Q: In case where this component is clearly not adapted, Can you propose to me another reference please ? 
 

Thank you in advance for your helpful return, 
Best Regards
Florent
  • The images link to your Gmail inbox. Please tell us your password. ;-)

    The pull-ups are disconnected; see [FAQ] If the OE pin is asserted to maintain Hi-Z at the IO, will it disconnect the internal pull-up resistors in TXS devices?

    The high output voltage is generated by the pull-up resistors, so any substantive load on the output will result in a voltage drop over those resistors. As long as the outputs are connected to high-impedance CMOS inputs, the output level will be sufficiently high.

    The specified VIL values are not the minimum switching threshold, but just a more-or-less random value that is used as a test condition for the specified VOL values.

    Typical logic FETs have a threshold voltage of about 1 V. This is not guaranteed.

    The TXS is a good choice for open-drain bidirectional applications. If you have unidirectional signals, a unidirectional or direction-controlled translator with proper buffers would work much better.

  • Hello Clemens, 

    Really thank you for your quick answers. 

    I have all the answers that I searched. 

    Sorry for the images I was not aware about that with the Gmail inbox. 

    Best Regards,