Thank you in advance for your helpful return,
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The pull-ups are disconnected; see [FAQ] If the OE pin is asserted to maintain Hi-Z at the IO, will it disconnect the internal pull-up resistors in TXS devices?
The high output voltage is generated by the pull-up resistors, so any substantive load on the output will result in a voltage drop over those resistors. As long as the outputs are connected to high-impedance CMOS inputs, the output level will be sufficiently high.
The specified VIL values are not the minimum switching threshold, but just a more-or-less random value that is used as a test condition for the specified VOL values.
Typical logic FETs have a threshold voltage of about 1 V. This is not guaranteed.
The TXS is a good choice for open-drain bidirectional applications. If you have unidirectional signals, a unidirectional or direction-controlled translator with proper buffers would work much better.
Hello Clemens,
Really thank you for your quick answers.
I have all the answers that I searched.
Sorry for the images I was not aware about that with the Gmail inbox.
Best Regards,