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SN74LV8153-Q1: data rate detection

Part Number: SN74LV8153-Q1

The part detects the data rate based on the timing of the two start bits.  Once that is determined, what is the tolerance on that for the rest of the data?

Thanks!

Matt

  • This device has an internal oscillator. It counts how many cycles elapse during the first start bit, and then assumes that the following eight bits have exactly the same length. So if the cycle count of the start bit is off by one (which can happen when the bit ends just between two cycles), the accumulated error at the last bit is eight cycles.

    The data bits are sampled in the middle, so the timing safety margin is the length of one half bit. At the highest baud rate, this is 1 / 24 kHz / 2 ≈ 20.8 µs.

    So the remaining tolerance is 20.8 µs − 8 × tcycle. Now we need to know the frequency of the internal oscillator.