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Original question:

Channel-to-Clock Skew clarification

TXS02612: Conflicting timing parameters: Channel-to-Clock Skew and Propagation Delay

Jason__B
Prodigy 10 points
Part Number: TXS02612

The switching characteristics table for VCCA=1.2V and VCCB=3.3V has conflicting timing parameters.

tPD (DATA to DATB) = 6.8ns

tPD (CMDA to CMDB) = 4.46ns

tPD (CLKA to CLKB) = 3.0ns

tsk (Channel-to-Clock skew) = 1.7ns

Can you please clarify how the clock and data propagation delays can vary by 3.8ns yet the channel-to-clock skew is listed as 1.7ns?

  • 0
    TI__Mastermind 42670 points

    Hey Jason,

    I would use the Channel to Clock skew spec as this will give the the difference between each output transitioning if their inputs were transitioned at the same time. The propagation delay spec typ value may be a little off based on the supply trend. Based on the architecture of the device, the 1.7 ns skew is reasonable versus a jump in propagation of 4.2 to 6.8 ns (2.5 V VCCB vs 3.3 V VCCB).