SN74LVC1G125-Q1: input rise/fall time over the spec, will cause output abnormal?

user3915702

Part Number: SN74LVC1G125-Q1
Other Parts Discussed in Thread: SN74LVC1G17-Q1

According to the datasheet, the input Max rise/fall time is 5ns/V, but in my design, it is 50ns/V, this will cause problem? like no output triggered? (no speed requirement for my design, only about 5M data rate)

over 3 years ago

0 Clemens Ladisch over 3 years ago

Guru 243980 points

This might damage the device. See [FAQ] How does a slow or floating input affect a CMOS device?

0 user3915702 over 3 years ago in reply to Clemens Ladisch

Prodigy 80 points

Thanks for quick reply!

Is there pin-to-pin part to replace SN74LVC1G125-Q1 to fit my design? with Schmitt-trigger or not CMOS buffer.

0 Clemens Ladisch over 3 years ago in reply to user3915702

Guru 243980 points

Do you need the OE input? The pin is N.C. on the SN74LVC1G17-Q1.

0 user3915702 over 3 years ago in reply to Clemens Ladisch

Prodigy 80 points

Thank you very much!

I believe this is a good replacement!

In my design, the /OE input is connected to GND directly, I think it's OK to connect pin 1 of SN74LVC1G17-Q1 to GND, though it is NC.

Logic

Logic forum

SN74LVC1G125-Q1: input rise/fall time over the spec, will cause output abnormal?