SN74LV595A: Output Pulled Up to 3V3 While VCC = 0V

Leo Rodriguez

Part Number: SN74LV595A

Hi Logic Team,

My customer uses the LV595A with a pull up resistor at the outputs to keep the output an a known-state at all times (avoid Hi-Z). If VCC = 0V while the outputs are being pulled up, will I have a potential reverse leakage through the high side FET of the push-pull output? If so, how much current can the FET handle?

Related to this, when would I expect Hi-Z output? From what I understand, only when OE is pulled high.

Thanks,

Leo

over 3 years ago

0 Clemens Ladisch over 3 years ago

Guru 243680 points

As shown in the Absolute Maximum Ratings table, voltages higher than V_CC are allowed in the high-impedance state (only when OE high) or in the power-off state.

0 Leo Rodriguez over 3 years ago in reply to Clemens Ladisch

TI__Intellectual 945 points

Thank you,

I'm guessing we will see reverse current from the output back through the high-side, correct?

Leo

0 Clemens Ladisch over 3 years ago in reply to Leo Rodriguez

Guru 243680 points

That current is specified as I_OZ and I_off.

0 Leo Rodriguez over 3 years ago in reply to Clemens Ladisch

TI__Intellectual 945 points

IOZ is specified with VCC = 5.5V, IOFF was the one I'm looking for. Thank you.

Just to verify, the device can support up to 5uA of reverse current. Anything north of that would not be recommended, right?

Back to the Hi-Z, I should not expect this state in any other scenario other that high OE - correct?

Leo

0 Clemens Ladisch over 3 years ago in reply to Leo Rodriguez

Guru 243680 points

"Support" is the wrong word. This is not a requirement but an electrical characteristic: when you apply a voltage of up to 5.5 V, then the leakage current will be less than 5 µA. (And that is the worst-case value at the most extreme temperature; expect some nA.)

A low leakage current implies that the pin has high impedance.

Logic

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SN74LV595A: Output Pulled Up to 3V3 While VCC = 0V