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SN74HC165: SN74hc165 Cascaded application CLK timing sequence requirement

Part Number: SN74HC165

Hi teams

My customer used two pics SN74HC165 as cascaded configuration. According to datasheet guideline two device CLK should tie together.

I have a questions about time sequence requirement for device1 shift its data to device2 through SER pin.

As two device using the same CLK signal, both of them will receive a edge signal to trigger one shot shift behavior. In the mean time device2 will also start to shift the SER PIN input data. But as there is a delay between CLK edge and QH pin signal output( it will be device2 SER pin input ). So if this delay is too long the data is not flip during shift the SER PIN input, it may lead to data loss in device2.

I wondering to know, should I add some cap in device2 CLK pin to add some delay between device1 CLK and device2 CLK to make sure the data signal is already setup up in device 2 SER PIN to avoid missing a data bit?

By the way, I also want to know what the third waveform mean for? Is it mean input signal should be ready (finished setup) before CLK edge signal?

What' the reference input mean for?

  • Hey Gabriel,

    No you should not add a capacitor, i would recommend looking at the timing requirements as these may give more details to work with.

    The waveform is just an example to show how setup and hold times are measured as well as rise/fall times. Its not info on application.

  • Dylan

    I do still not figure out the timing requirement in datasheet. 

    What I want to know is if the SER input signal rising edge is much slower than CLK input signal. 

    Or on the other words, the device received the order from CLK to shift the SER signal/data into the device before the SER signal buildup properly.

    Like below waveform:

    As in cascaded configuration, DEVICE1 QH output signal buildup for device2 SER input at least for tpd delay even without the cap.

    How this device make sure that SER input signal already buildup when the CLK edge signal comes?

  • Hi Dylan

    Could you take some time to look at this, its a business essential case.

    I also want to know are SER input signal should buildup before the SER pin received the edge signal from CLK?

  • Have a look at the logic diagram (figure 3). The connection between the first device's QH output and the second device's SER input is exactly the same as the connections between the internal flip-flops (which also share the CLK signal). At each clock cycle, each flip-flop receives the previous state of the preceding flip-flop. The tpd value tells you how long you have to wait before you can send the next clock.

    Connecting two devices together creates a simple 16-bit shift register; the SN74HC165 was designed to work this way.

    Please note that the minimum fmax and the maximum tpd pretty much correspond with each other; if your circuit slows down the SER edges (i.e., increases tpd), then the frequency that you can use decreases accordingly.


    Thanks for your comments.

    I also want know after the device received an effective CLK edge signal and start to shift the input data from SER pin, the needed setup and hold time for sample is at least 15ns base on below datasheet spec is that right?

  • The propagation delay time plus the set-up time must be shorter than the clock cycle. (This is an restriction on the frequency you can use.)

    The propagation delay time must be longer than the hold time. (This is a property of the device itself.)