Hi,
according to the datasheet the absolut max input voltage VI is -0.1 to 6.5V and VO even in unpowered state is allowed in teh same range.
Does this mean that any logic level below 6.5V would not damage the device even if power is not available? Or in other words, the ESD clamps and substrate diodes do not cause low impednace in unpowered condition?
Is there any specification or a rough estimation for the imput impedenace in unpowered state?
I assume that the SPICE model is only valid in powered state, correct?
Günter