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SN74AVC2T245: Dmic data cannot be transmit to HOST properly.

Part Number: SN74AVC2T245
Other Parts Discussed in Thread: SN74AXC2T245, SN74AVC2T244

Hi Sir,

We encountered a weird issue on customer factory they reported they designed SN74AVC2T245 for Dmic level shift 1.8v (PCH) to 3.3v (Dmic module).

But some of DUT not present the proper data from Dmic to PCH, but actually CLK can be delivered to Dmic.

Here are some testing customer did, but not fix:

1. Swap the other brand p2p level shift then works correctly.

2. Re-attach the Dmic module sometimes will become normal.

3. The failure DUT will always encounter the problem.

4. Remove the ESD, EMI solution and any resistors on Dmic PDM DATA/CLK.

Here comes some question would need your support to clarify more:

1. Customer figured out some of DUT will send some noise when boot. They afraid it would cause the problem. What is the V low on input side? If level is low... we should not open the trace and output anything right? 

Yellow is B side (3.3v) and Blue is A side (1.8v), meanwhile... 1.8v is low around 0.4v or more lower (this picture not capture with the correct moment)... for the case, the noise should be output?

2. Dmic PDM CLK is working on 2.4MHz... SN74AVC2T245 should not be the problem to handle this clock rate, right?

3. CLK can be delivered properly, but Data is not present out from Dmic... any idea or experience to cause this case? 

Looking forward to hearing from you soon, any comments will be appreciated.



  • Show the schematic. At which points did you measure?

  • Hello, 

    Please provide the schematic for review. This device will be able to support 2.4MHz without issue. The device will not treat CLK or DATA any differently and should be able to operate at the speeds you are talking about.

    Is there anything else connected to the output that could be causing this noise?

    If you zoom out in time, does the output eventually settle or is it still stuck at VCC/2?

    In addition to the question that Clemens and I asked above, would you also consider changing to our SN74AXC2T245.

    If there is concern about noise on boot up, we have recently released this updated device for which we have done extensive testing to enable the following feature: Glitch-free power supply sequencing allows either supply rail to be powered on or off in any order while providing robust power sequencing performance.

    Please consider ordering samples or units from the product folder to see if this newer device (which is p2p) helps to alleviate this issue:


  • Hi    

    Thanks for the support, how to send you the privated mail for the schematic check?

    BTW, I got the main question from customer that they would like to know if the input side of SN74AVC2T245 under the V low... the output should expect keeping low or high?



  • Hey George,

    We don't need the whole schematic, just a snippet of our device and everything that is connected to the channel that has issues. Will that enable you to post it in this thread?

    If the input is ≤ Vil, then the output would be low.

  • Hi Sir,

    I think it should be no problem that shared the partial schematic... please help to check if there is any concern?

    Customer concern we are not follow the Vil spec, when the signal below the Vil... then signal should not be send by output, is it correct? 

    But now, they can observe the noise from B-side with the low level off-set on A-side.

    BTW... Would it be concern that input side got any off-set voltage?

    Currently, they have tried to pull-low the CLK on the input side, then issue seems gone, they are going to do few more DUT rework to see it would getting help or not. For this case, did we have any concern for the pull-low solution on input?



  • Hey George,

    Are all the passive components populated (more specifically R9124 and R9125)? I'm not really seeing a DNP designation or something similar.

  • Hi Sir,

    If there is the * before the components then means DNP. So, as this case, R9124 have been mounted and R9125 unmounted.

    Please let me know if there is any incorrect.



  • Hey George,

    Thanks for the info I see that now. As for your previous question a constant offset voltage could potentially damage the device especially if it has an amplitude close to 1/2 Vcc. This would incur high currents that could potentially harm the device. I'd recommend doing an A-B-A swap to see if the issue follows the device, then we can confirm if damage is causing the observed issue.

  • Hi Sir,

    I have checked the behavior by using the SN74AVC2T244 EVM, but I saw the signal are not good for the CLK source.

    Please refer to the scoop screenshot, the CLK rate is i2s BCLK around 3.07MHz...and come from Audio Precision.

    Input on A1 port (1.8V) and B1 be output side (3.3V)

    It should be within our spec... but what I saw the CLK signal with very large over-shooting...and sometimes the noise will cause on raising/falling edge.... would it be expected as your experience?

    Any comments will be appreciated.



  • Hey George,

    That's almost 14 Vpp of ringing on the falling edge, this is definitely not expected. I'm assuming there is no load? Do you have active probes to measure this? Did you add some bypass caps to the supply?