Other Parts Discussed in Thread: CD4046B, SN74LV4046A
We need to use the CD74HC4046 in an already successful design of an instrument that uses an HCF4046, as the HCF4046 is now unobtanium. The PLL is used with a TI CD40103BE to make a 100X frequency multiplier.
VCC is 5V.
Pin 14 input is a 5V square wave (50% duty cycle) ranging from 128-2048 Hz.. Thus the PLL output on Pin 4 is 12,800-204,800 Hz.
PROBLEM: No matter how we configure it, either the high or low end of the frequency range is unstable. The output is stable enough for a frequency counter, but the instability is seen on the scope as a fast vibration, either shaking the waveform itself, or displaying a ghost wave out of phase with the bright waveform. The instability occurs when the voltage at Pin 9 is below 0.9V or above 4.53 volts. This is close to the limits noted in the spec sheet, that states that Pin 9 (VCOin) should be kept between 0.9 and 4.1 volts.
QUESTION: For this frequency range, what is needed to assure that Pin 9 is kept between 0.9 and 4.1 volts?
QUESTION: Spec sheets indicate this PLL is capable of 100,000:1 frequency range. Our requirements are only 2048/128 a 16:1 frequency range. How can we fit that into 0.9-4.1 volts on Pin 9?
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I've tried various values, and the following two independent cases come closest to working.
C1: Case 1 = .06 uF, Case 2= 220pF
R1: Case 1 =3.9K, Case 2=200K
R2=NC (infinity)
R3: Case 1 and Case 2 =100K (PIn 13 to Pin 9)
C2: Case 1 and Case 2 =22uF (loop filter capacitor)
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Thank you in advance for your help.