SN74LVC1G07: SN74LVC1G07 Design Issue

user6317889

Prodigy 80 points

Part Number: SN74LVC1G07

Dear Sir,

Is there any risk about this design. When the input signal voltage is 3.3V, the VCC of 74LVC1G07 is only 1.8V?

over 3 years ago

0 user6317889 over 3 years ago

Prodigy 80 points

0 Clemens Ladisch over 3 years ago in reply to user6317889

Guru 243220 points

See [FAQ] Can the input voltage (Vi) to my logic device be higher than the supply voltage (Vcc)?

0 user6317889 over 3 years ago in reply to Clemens Ladisch

Prodigy 80 points

Dear Sir,

Thanks for you help!

The SN74LVC1G07 IC without positive clamp diode, so the voltage of input is 3.3V will not affecting the VCC(1.8V). So the design is OK. I'm right?

Thanks!

0 Clemens Ladisch over 3 years ago in reply to user6317889

Guru 243220 points

Yes.

0 Michael J Schultis over 3 years ago in reply to Clemens Ladisch

TI__Mastermind 24485 points

Hello,

Yes, that is correct. Since the input is overvoltage tolerant (without positive clamp diodes), it can be overdriven up to the VI (input voltage) recommended maximum specification without issue.

Best,
Michael

0 user6317889 over 3 years ago in reply to Michael J Schultis

Prodigy 80 points

Dear Michale,

Worst case for logic low on MCU is 0,5V, minimum required input level on buffer(SN74LVC1G07) is 0,63 V (if buffer is supplied by 1,8 V), there is 0,1 V of margin. The question is how buffer will work during extreme temperature condition, on bigger population and during ALT test.

Thanks!

0 Dylan Hubbard over 3 years ago in reply to user6317889

TI__Mastermind 42600 points

Hi,

The spec in the data sheet accounts for this.

Logic

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SN74LVC1G07: SN74LVC1G07 Design Issue