Quickly find solutions to common questions about voltage translation (level shifter) devices by clicking this link. This FAQ answers the most common questions asked about these devices …… ……… …
|Input Parameters||Output Parameters|
|Power and Thermals||Timing Parameters||Logic Technology||Quality and Manufacturing
- [FAQ] How do the LSF translators work?
- [FAQ] What is the difference between TXS TXB and LSF devices?
- [FAQ] If the OE pin is asserted to maintain Hi-Z at the IO, will it disconnect the internal pull-up resistors in TXS devices?
- [FAQ] Are there voltage level translation / level shifter device recommendations for the industry standard interfaces like GPIO, SPI, UART, I2C, MDIO, RGMII, I2S etc?
- [FAQ] What is the TXS device internal resistor variation/ tolerance
- [FAQ] What are the power sequencing requirements for the translation device?
- [FAQ] What should be done with unused I/O pins of the level translator devices?
- [FAQ] Why are the TXS01xx VIH/VIL specifications so stringent?
- [FAQ] Why is there a voltage offset at the input of the SN74AXCxTxxx device?
- [FAQ] Is there a naming convention for Level Shifters?