Other Parts Discussed in Thread: SN74HCS72
I have a customer considering D-FF for a clock sync setup.
But they either need <5ns tpd or >10ns tpd for propagation delay from xCLK to Q
The DS lists the Max/Min over temp given different CL values...
1. Based on section 6.9 (-40℃~85℃), is it safe to say that for max CL of up to 50pF (including probe/jig capacitance when measuring), the maximum tpd for VCC = 5V over temp/process will be under 4ns, and the minimum tpd will be greater than 1.5ns?
If so, then there should be no problem achieving tpd <5ns with the above device, correct?
Is the above understanding correct?
2. In case the customer stacks 2,3 D-FF to get MTBF higher than product lifecycle, the MIN tpd would only be 1.5ns + 1.5ns + 1.5ns = 4.5ns
Is it possible to increase CL or do something, to ensure the minimum tpd over temp/process is > 3.5ns?
(If VCC = 1.8V, it looks like at 50pF the MIN tpd is 2.7ns...but then can't support CLK of 32.768MHz...)
If you know of any other small package devices, that support >32.768MHz CLK and VCC = 5V, with tpd >10ns (SN74HCS72 Schmitt trigger was one option, but there is no detail regarding minimum prop delay over temp) that would be helpful.