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SN74LVC1G07-Q1: High Current Buffer

Part Number: SN74LVC1G07-Q1
Other Parts Discussed in Thread: SN74LVC3G07-Q1, SN74AVCH8T245, SN74AVC8T245

Hi experts,

We have a customer that is looking for 10-15mA source/sink at 1.8V. I see lots of buffers that support the 1.8V level but the max current is in the 4-8mA range.

Is there any high current, low voltage digital buffers?

If no, could I connect TWO inputs and outputs of a buffer to double the current?

THanks,

Connie

  • Hi Connie,

    At what output voltage do they need to sink 10 to 15mA?

    The test current (IOL) is what is forced into the output, and the output voltage (VOL) is what's measured:

    Here you can see that the output voltage will be a maximum of 0.45 V with a sink current of 4 mA.  From that we can get a worst-case resistance at the output of 0.45/.004 = 112.5 ohms. Then, using that value, we can determine the voltage drop at 10mA or 15mA:

    15mA * 112.5 = 1.687 V

    10mA * 112.5 = 1.125 V

    I wouldn't consider these valid "low" output values for a logic device, but if the goal was to just sink 15mA, then it would work.

    You can use a multi-channel device to increase the output drive strength - for example, the SN74LVC3G07-Q1 could be used with all three channels in parallel, which would result in an output impedance of 112.5/3 = 37.5 ohms. Doing the same thing again:

    15mA * 37.5 = 0.56 V

    10mA * 37.5  = 0.38 V

    These are starting to get more reasonable.

    Can you tell me what the customer is trying to do? Why are they sinking 10 or 15mA into a 1.8V open-drain buffer?

  • Hi Emrys,

    Thank you for showing me the calculation.

    My customer offer a board that has 144 I/O and uses the the 74LVC8T245 buffer/voltage translator. The customer can select the user I/O level (VCCB) to be 1.8V, 2.5V, 3.3V or 5V.The VCCA level is always 3.3V since these signals interface with their FPGA. Their customer need a 1.8V interface to be able to source/sink 10-15mA, a link to their card.

    They have 1.8V logic, but I don't know what the logic thresholds are. 

    I don't see calculations for 1.8V only 1.65V, would you be able to estimate the Voh and Vol values at VCC=1.8V and source/sink at 10mA or that is the closest data we have?

    Are there any better options? They have high I/O count, and this would mean all channels on the buffer would source/sink this amount of current in case there is a collective issue.

    Thanks,

    Connie

  • Hi Connie,

    I think there are two FAQ's that will help you out:

    [FAQ] How do I determine the output voltage (VOH, VOL) or output current (IOH, IOL) of a CMOS logic device?

    [FAQ] What method is best used for estimating specification values between those given in the datasheet?

    To answer the question of "are there any better options" -- to drive an unknown load at 1.8V and 15mA? Sure - discrete individual FET drives could do it. TI doesn't sell those though, so I can only recommend paralleling channels as I described above.

  • Hi Emrys,

    Thank you for the link. I explained the issue and provided the calculation to the customer, and they said 8mA should suffice.

    Based on this new info the SN74AVCH8T245 should be able to meet their needs.

    Is there any issue with using all 8 outputs at 8mA? Junction temperature considerations? Is there a total I limit?

    I am not sure if the continuous output current is spec for sum of all channels. 

    Thanks,

    Connie

  • Hey Connie,

    Max junction temperature almost never becomes a concern with logic devices unless there are a lot of channels switching at high frequencies.

    All current going to (or from) an output pin must also go through a supply pin - ie if all 8 channels are sinking 8 mA, then there's 64 mA flowing through the ground pin (plus a small amount of Icc).  There's a spec for this in the abs max table here:

    The bus-hold circuit will add some complexity to the system -- if they aren't sure what's being connecting to it, then it could cause problems. There's more info on exactly what 'bus hold' means here (Figure 9 in particular is useful for reference): System Considerations For Using Bus-hold Circuits To Avoid Floating Inputs

    I would recommend to go with the simpler SN74AVC8T245 -- unless the bus-hold is required.

  • Hi Emrys,

    Thank you for your help!

    Connie