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CD54HCT4046A: Debugging help with CD54HCT4046A

Part Number: CD54HCT4046A
Other Parts Discussed in Thread: CD74HC4046A, LMC567

Hi team,

I am posting this on behalf of our customer regarding debugging help for CD54HCT4046A.

Please see their inquiry below:
"We attempted to use the CD54HCT4046 as an alternative to the LMC567 as it is military standard. However, the output is nothing like I anticipated. I used the following paper from TI "Implementation of FSK Modulation and Demodulation using CD74HC4046A". As per the datasheet for CD54HCT4046, I believed the application report could apply to this part.

I need an FSK demodulator with the logic high frequency being 62.5kHz and the logic low frequency being 83.3kHz. From my understanding, the output logic might need to be inverted with a different part but I'm not concerned with that for now. I attached the three designs I attempted as well as the design equations I used."

Here is the output from the DEMOD pin (pin 10). I can see it is locking and creating an output proportional to the input frequency, which is what I expect. However, I expected the DEMOD output to not be sinusoidal or have lower peak-to-peak ripple. Any advice?

Please let me know your questions or comment on the above inquiries.



  • Hi Jonathan,

    I can take a more detailed look in the morning, but for now can you tell me what I'm looking at here? What are the two signals shown? Is one AC coupled?

    I'd also like to get a faster view to see the actual waveforms (this view is good for envelope, but I can't see the signal here).

    I'd also like to get a look at the input signals to the comparator and the comparator output (before and after the filter), if possible.

  • Hey Jonathan,

    I think I see the trouble now - why are they AC coupling the single-ended signal input of this device?  This is commonly done in RF circuits, but this is a digital logic circuit. This device has CMOS inputs, and needs to have clean 0 to 5V (or 0 to 3.5V)  fast-transitioning digital inputs at the SIG_IN pin.

    These capacitors will only allow through the AC waveform, which will cause problems.

    * Correction - this device _does_ support ac coupled inputs due to a self-bias circuit at the input. I was wrong.

  • No. The datasheet states: "A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers". The input capacitors are not the issue. I am concerned with the low pass filter present on pin 9. The datasheet isn't clear on how to select the low pass filter for FSK applications.


  • Hello and welcome to the forums!

    That's very interesting - thanks for pointing that out. Not all of our '4046 functions include that feature, so sorry about the misinformation there. I'll edit that out to avoid anyone else getting confused by my mistake.

    I would typically select a LPF based on the lowest expected PC2 output frequency, and reduce the corner frequency by two orders of magnitude to get the cleanest output possible.  This may not respond fast enough for your system though.

    I would use PC1 if possible, then you can add an active filter with the same cutoff. We're essentially just filtering PWM to ~DC in this case.

    You haven't really provided me with what the problem is. Can you please expand on the issue? All I have is "the output is nothing like I anticipated"  and that doesn't really tell me much. Is the frequency incorrect? Waveform issues?

    I can see that the one of the above waveforms has an odd envelope to it, but I don't know what that waveform is / where it was measured - and I can't see the individual waveforms, just a very zoomed out shot.

    What does the input to the VCO look like (after the filter)? What does the output of the phase comparator look like?

    I have 100 questions, but if you can give me more details, maybe we can narrow that down significantly.