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SN74LVC1G08: Outputs going above VCC, what is allowed?

Kannan Sockalingam
Intellectual 1490 points
Part Number: SN74LVC1G08
Other Parts Discussed in Thread: SN74LVC1G34, SN74AUP1G08

Team, working with someone on this device. The datasheet indicates that “Outputs should not be pulled above VCC” but once VCC=0, there can be a voltage on the output.  Their implementation (shown below) has a pull-up on the output (VBATT=3V3).  During operation, VCC_3V3 will shut down, and VBATT will remain high.  Will this short period that the output exceeds VCC during shutdown cause any damage to the part or any other issues?

 

  • 0
    TI__Guru* 96591 points

    Hi Kannan,

    No, this won't cause any problems.

    It looks like they're trying to  buffer a signal, but only if VCC_3V3 is available. If that's the case, I would recommend to use the SN74LVC1G34 instead. They can continue to use this device if it's better for them, but I thought I'd put it out there that there's a buffer available, too.

  • 0 in reply to Emrys Maier
    Prodigy 20 points

    Hi, I am trying this implementation out, and when I turn off VCC_3V3 I am noticing the output goes low for a brief moment before being pulled high (despite the pull-up on the output).  Any ideas why that would happen?

    For additional information, the L_Z_L signal comes from an FPGA that is powering down as well, but I have tried to add a pull up to VCC_3V3 on that signal and still see the same issue.  The output feeds into another  SN74AUP1G08 that is always on.  

  • 0 in reply to Jessica Urbano1
    TI__Guru* 96591 points

    Hi Jessica,

    I would recommend to monitor pins 1 2 and 4 during the power-down event to see exactly what's happening.

    Most likely, the input at 2 is going low before the supply at 1 & 6 is low enough to shut off the device, which would cause the output to switch low.

  • 0 in reply to Emrys Maier
    Prodigy 20 points

    Hi Emrys-

    That was my initial assumption as well, but I figured adding a pull up from pin 2 to VCC_3V3 would prevent this as the inputs would go low the same as VCC_3V3.  I have monitored both pin 1 and 2 and they look about even.  Also from my understanding, the gate will shut off at 1.65V, but a "low" on the input is anything below .65*VCC.  So if the inputs and VCC are close, the gate should shut off before the input is seen as a low.  Is there anything else that could be causing this? 

  • 0 in reply to Jessica Urbano1
    TI__Guru* 96591 points

    The device will not turn off at 1.65V -- it is just no longer guaranteed to function below 1.65V. These are analog devices, so as long as there is sufficient voltage to bias the transistors, they can be actively driving the output.

    Can you get a scope shot of both inputs and the output together during power down & post here?