In section 7.2, why don't we have negative voltage spec of V(ESD) spec of HBM and CDM?
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The SN74LVC1G04 uses the same type of ESD protection as almost all other CMOS logic devices in TI. The values provided are the magnitude of the ESD strike and don't indicate polarity.
This is related to the changes in formatting standards for datasheets and doesn't affect the performance of the device. Fortunately, the new standards include the "±" symbol to avoid confusion.