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SN74LVC16T245-EP: How to define buffer Input state

Part Number: SN74LVC16T245-EP

Hi All,

In my Project I am using one 16 bit level translator SN74LVC16T245MPWREP, one 8 bit level translator SN74LVC8T245MPWREP, one 2 bit level translator SN74LVC2T45MDCTTEP in which signals are connected to a Micro D connector for both Inputs and outputs. My questions are

  • If the connector is not mated with other system, will the I/Os are in Hi-Z state.
  • If they are in Hi-Z state, Is it safe to remain it in same state or I should define the state of the I/Os by pulling up or down.
  • In the datasheet of SN74LVC2T45MDCTTEP, I am unable to find Ɵjb and Ɵjc values.Can you Please provide the values.