Other Parts Discussed in Thread: SN74LVC16373, SN74LVCZ16245A
My customer made the following circuit using two logic ICs with bus hold. The direction shown in Figure 1 (DIR = Low) works correctly.
Q1: If you switch to the direction shown in Fig. 2 (DIR = Hi), the hold voltage will be 2.4V. Is this the correct operation?
I think 3.3V is correct because the hold circuit holds the voltage just before the input becomes Hi-Z.
Q2: Normally, I think that 500uA x2 is required to drive two hold circuits with one I/O. But the CPU is always INPUT.
When switching directions, I think the output current of the SN74LVCHR16245 is driving its own Hold circuit. Is this explanation correct?
The Hold voltage is apparently 2.4V, but the output is 3.3V so the circuit works fine. However, since the Hold voltage is not theoretical, they are afraid that it will malfunction due to some influence.
(SN74LVC16373 : incorrect --> SN74LVCH16373 : correct)