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SN74LVCHR16245A: with SN74LVCH16373

Part Number: SN74LVCHR16245A
Other Parts Discussed in Thread: SN74LVC16373, SN74LVCZ16245A

Hi,

My customer made the following circuit using two logic ICs with bus hold. The direction shown in Figure 1 (DIR = Low) works correctly.
Q1: If you switch to the direction shown in Fig. 2 (DIR = Hi), the hold voltage will be 2.4V. Is this the correct operation?

I think 3.3V is correct because the hold circuit holds the voltage just before the input becomes Hi-Z.

Q2: Normally, I think that 500uA x2 is required to drive two hold circuits with one I/O. But the CPU is always INPUT.
When switching directions, I think the output current of the SN74LVCHR16245 is driving its own Hold circuit. Is this explanation correct?

The Hold voltage is apparently 2.4V, but the output is 3.3V so the circuit works fine. However, since the Hold voltage is not theoretical, they are afraid that it will malfunction due to some influence.

 

Fig.1

Fig.2

(SN74LVC16373 : incorrect --> SN74LVCH16373 : correct) 

Regards,
Hiroshi

  • Hello Hiroshi-san,

    Generally, it is recommended to put the entire device in Hi-Z mode before switching the direction.

    Is it possible to do this, and if so, does that fix the behavior?

    Otherwise, if the hold circuit is holding the line high, it does seem odd that it wouldn't drive to the rail. The only reason it would not would be because there is some external source of leakage. The bus hold is a relatively weak circuit. Is the line truly Hi-Z, or does the GPIO on the CPU maybe have an integrated weak pulldown?

    Best,
    Michael

  • Hi Michael-san,

    Thank you for your quick reply.

    >>Generally, it is recommended to put the entire device in Hi-Z mode before switching the direction.

    Does that mean changing port B on the SN74LVCHR16245 from Logic Hi to Hi-Z before switching directions?

    This IC controls the data read / write of the flash ROM. Therefore, it is theoretically possible to change Port B to Hi-Z, so I will propose it to them.

    Regards,
    Hiroshi

  • Hiroshi-san,

    To be more precise, it would mean changing the entire device to Hi-Z using the device OE input before changing the direction.

    I still feel it may be more likely that something is trying to drive the line low which isn't allowing the bus hold to get to 3.3V. Is there no other weak pulldown on that line? Many CPUs have integrated weak pulldowns.

    Michael

  • Michael-san,

    Thanks a lot.

    >To be more precise, it would mean changing the entire device to Hi-Z using the device OE input before changing the direction.

    I understood and check for weak pulldowns.

    Regards,

    Hiroshi

  • Michael-san,

    I'm sorry to keep you waiting.

    The existence of the pull-down in MCU has been confirmed.
       Minimum 7k ohm to maximum 14k ohm.

    I checked the App Note SCLA015B page14.
    According to this, I think that 3k or less is acceptable.
      * at  Vcc = 3.3V  (3.0Vmin).

    So I don't think this circuit works properly.
    Is this conclusion correct?

    Regards,
    Hiroshi

  • Hi Hiroshi-san,

    Yes, that is correct. I would recommend to switch to a non bus-hold device to support the internal pull-downs.

    I think SN74LVCZ16245A is the closest match without bus-hold inputs.