Other Parts Discussed in Thread: SN74HCS245-Q1
Please can you address a reference design making use of SN74VMEH22501?
Please can you address decoupling recommendation for this device?
Many thanks
Andrea
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Please can you address a reference design making use of SN74VMEH22501?
Please can you address decoupling recommendation for this device?
Many thanks
Andrea
Hey Andrea,
I do not have any reference designs for this part, but as for decoupling I recommend a .1u F cap close to the Vcc pins. Are you looking for this device specifically or just a standard transceiver?
we are currently using this transceiver in many projects, We are always facing problems of switching noise, light or severe;
we use these transceiver not specifically in a VME system, but on a generic parallel bus based system.
I would like to have a design guide that, once for all, clears the noise issue.
For instance:
1) on a board we are using qty 3 transceivers, and for each of them we are using 5x 0.1uFx, 5x 10nF, 2x 10uF, in order to cover a larger spectrum; these caps are very close to the device.
2) we have not any specific circuit to treat VCC bias pin, we are treating it as regular VCC pin
3) we are not using clk and latch capability, so we stuck CLK to 0 and LE to VCC
4) we are sticking to 0 all unused input/outputs where OEAB and OEBY are stuck to VCC
3) we are using near end and far end termination with 330 ohm pullup to 5V and 470 ohm pulldown to GND
When the bus is quite i don't see any noise both on 3.3V an don the 5V.
When i start toggling the bus (hard toggling: all '0' to all'1' and viceversa) i see switching noise, and sometimes it is disruptive for the bus.
In some case a noise over a signal is triggered by the buffer ! thus transferring a wrong logic level.
best regards
Andrea
Hey Andrea,
Do you have any scope shots you can provide so I can see the noise?
Hello
we have partialy solved the noise problem
It was caused by the absence of adequate CAP on the backplane, close the NEAR END terminations (i.e.: at the end of the backplane)
We added many 22uF to the 5V near the termination and now the noise is under control.
Moreover we used traditional probe + gnd tail to catch the signals, and the size of the ground loop caused a lot of radiated noise to be triggered on the scope.
Instead we used a very tight loop coaxial cable soldered on the test point with a local ground very close to the signal and so we saw the real face of the signal.
And infact after addind the CAPS on the 5V and after probing the 5V as said above we see a very stable 5V with <15mV ripple, which is very ok.
Now we are facing another problem due to excessive ringing of a signal across the buffer, as shown in the picture below.
The waveform below is the backplane side, and we assist to a huge ringing.
Question:
we have a 60ohm track which is terminated on a couple of 470pulldown/330pullup located at the two side of the backplane (near the source and near the end, as recommended by datasheet).
But the termination does not match the track impedance, so we see ringing.
What is the best solution?
We have added 33ohm series resistor (in addition to the 26ohm embedded on the chip), in order to have around 60ohm
In this way we cleared very well the ringing and the signal is very well defined. But we are seeing that the logic 0 is not at 0V but there is a offset of around 0.8V, due to the current flowing into the series resistor.
We can cope with this offset, but i wonder if there is an alternative solution, for instance using a bead instead of the 33 external series resistor...
best regards
Andrea
Hi Andrea,
Driving long transmission lines has been an issue in logic more many years.
The absolute best solution for preventing reflections is to impedance match the source, transmission line, and load. This will also cut your max signal voltage in half at the receiver.
The compromise is to dampen reflections at the source with the series output resistor. You can try larger values, which will result in slower edges and less high frequency noise content in the signals -- but it also slows the signals, which would be problematic for your application.
The best solution I know of is to use the series resistors that you've already described. I have a more detailed explanation here: [FAQ] What happens when I connect a logic device's output to a 50 ohm transmission line?
Hi Andrea,
Thanks for the scope shots. It looks to me like those confirm that improving your impedance match will reduce ringing, but it also shifts your voltage.
One way to avoid the voltage shift is to add a series capacitor with your termination resistors, blocking DC current. This will cause the signal to smooth out without shifting the DC voltages.
The down side to this approach is that the RC circuit will slow the signal edges. Here's an example circuit built in ADS for signal integrity simulation. I used a very simple transmission line model to just show the effects.
The highlighted section shows the RC filters. Before simulating, I swapped out the "VIN" name to "TRIGGER" for clarity.
The simulation of a perfect transmission line gives a tell-tale 'stair step' appearance to the signal -- real signals rarely look like this. If you have a full model of your board, traces, connectors, etc. they can be loaded into an IBIS simulator to improve the accuracy. I only did this to show for an example.
The red waveform is with the termination resistors essentially removed (1 MOhm), which shows a strong reflection on the line.
The blue waveform shows the termination resistors added at 120 Ohm, which smooths out the reflections and makes the signal monotonic.
Hi thanks for quick feedback.
Questions:
1) Isn't termination supposed to let the buffer work sinking/sourcing DC current to improve noise immunity? DC blocking caps don't allow this DC current...
2) datasheet recommends 470/330 thevenin termination on 5V. Setting Z voltage to around 3V, quite near 3.3V. Your design uses 120/120 thevenin on 3.3V, thus setting Z middle point at Vcc/2. Why this difference? What is recommended termination?
3) could a bead instead of 33R series be used? Thus not shifting the offset.
Just as a general I formation: our backplane uses 3 IO slots + a Master CPU slot
Hi Andrea,
Andrea Guitta said:1) Isn't termination supposed to let the buffer work sinking/sourcing DC current to improve noise immunity? DC blocking caps don't allow this DC current...
I'm not aware of any noise improvement due to increasing the DC current through the output driver for a CMOS device. I guess you could call the DC shift in the output some improvement in the overshoot / undershoot, but it's not _really_ an improvement... just shifting the signal. If you have any reference, I'd be interested to read more about this.
Andrea Guitta said:2) datasheet recommends 470/330 thevenin termination on 5V. Setting Z voltage to around 3V, quite near 3.3V. Your design uses 120/120 thevenin on 3.3V, thus setting Z middle point at Vcc/2. Why this difference? What is recommended termination?
Yes, that's the typical VME64x bus configuration shown in the datasheet. I wouldn't call it a recommendation so much as an example of a common use-case.
For your application, you mentioned that the system is operating with Zo = 60 ohms, so I used a 60 ohm thevenin termination (120 ohm parallel with 120 ohm).
The device doesn't have a perfectly balanced output, with the negative driver being stronger than the positive one, so offsetting the termination resistances offers a more 'balanced' signal output. With the added blocking capacitors, this is less of an issue.
Andrea Guitta said:3) could a bead instead of 33R series be used? Thus not shifting the offset.
I haven't ever seen this attempted, so I don't know if there would be any negative effects. Theoretically it would work as long as you could dampen out the higher frequency components of the signal, typically in the > 300MHz range.
1) in your proposed circuit the DC current sunk/sourced by the buffer only flows through the 10Mohm (R2) resistor. is this resistor required for the real design or only for the simulation?
2) based on the circuit proposed by you, are you stating that the buffer works well, too, with basically 0 current flowing from the driver?
3) i am not quite familiar with AC thevenin termination, using CAPS both on +3.3 and on GND. It seem like you are only caring about AC termination, neglecting DC effects. In this case what is the reason of having RC on TOP, too? would it be enough having RC termination only to GND? for instance: 60ohm + 100pF to GND
4) by using the above mentioned 60 ohm equivalent AC termination, why is it necessary having 33 series near the driver, too?
5) oppositely, could only 33ohm series resistor (without thevenin at the ends) be used?
Many thanks for cooperation
Andrea
Hey Andrea,
Andrea Guitta said:1) in your proposed circuit the DC current sunk/sourced by the buffer only flows through the 10Mohm (R2) resistor. is this resistor required for the real design or only for the simulation?
The 10 Mohm resistor + parallel 5 pF capacitor is just there to represent a typical CMOS input. I use it in most of my sims.
Andrea Guitta said:2) based on the circuit proposed by you, are you stating that the buffer works well, too, with basically 0 current flowing from the driver?
Yes, the device will hold the signal at either rail without an active current draw at the output.
Andrea Guitta said:3) i am not quite familiar with AC thevenin termination, using CAPS both on +3.3 and on GND. It seem like you are only caring about AC termination, neglecting DC effects. In this case what is the reason of having RC on TOP, too? would it be enough having RC termination only to GND? for instance: 60ohm + 100pF to GND
Yes, that might be a better option. I'm just providing options.
Andrea Guitta said:4) by using the above mentioned 60 ohm equivalent AC termination, why is it necessary having 33 series near the driver, too?
For proper signal transmission without reflections you need a matched source, transmission line, and 60 load. The added output resistance is intended to help match the source to the t-line and load.
Andrea Guitta said:5) oppositely, could only 33ohm series resistor (without thevenin at the ends) be used?
Yes, that is a common method (shown in the link I provided a few posts back). It's not always effective though, so added filtering can help.
Hi Emrys, many thanks for support and detailed answers.
So why is SN74VMEH22501 special with respect a standard '245 buffer?
Hi Emrys
i confirm that after implementing your suggested termination we have very well improved the signal integrity.
Below the circuit, with 33ohm series close to the driver and 64.9ohm + 27pF at both ends of the transmission line
The ringing is less than 50ns in time and less than 500mV in amplitude.
We are very satisfied about results; we can improve further by best tuning AC termination
Many thanks
Andrea
Hey Andrea,
Thank you for posting the results! I'm glad to see that you've been able to resolve the issue.
Andrea Guitta said:Hi Emrys, many thanks for support and detailed answers.
So why is SN74VMEH22501 special with respect a standard '245 buffer?
Hi Emrys,
just to close the Ticket, i want to share last details:
We tried different termination values on three different signal, in order to see at the scope the differences.
All the three signal have 33ohm series resistor placed near the driver
Waveform #1 and #2 have quite similar AC termination
Waveform #3 has no termination at all
We see that a big improve is given by the series termination; instead load termination seems to have very slight impact.
Does it make sense to you?
Generally speaking, all the waveforms look great to me, with very low under/overshoot and with <10ns rise time, what's our opinion?
Best regards and many thanks for support
Andrea
Hey Andrea,
Yes, in my experience just having the series resistors is enough in the vast majority of systems. The other options are really there if that doesn't work well enough for you.
It seems that the added pull-up/pull-down terminations were causing the majority of your problems.
Just curious - have you tried reducing the 33 ohm series resistor to 0 to see what it's like without it? I'm guessing the ringing would be a bit worse, but it probably wouldn't be too bad since the device already has internal resistors.
Hi Emrys
sorry for delay. Reducing series R to 0 causes some ringing anyway, event down to -1V, which is not very good for the device... even if the communication works well
So we decided to leave 33R and this definitely fixes the issue and waveforms are pretty good.
I am writing to you again for another question.
Currently our backplane has no termination at all, and only 33R series are used, bot on CPU board and on all I/O boards (12 in total)
I have a probe on a data signal on the backplane
With zero board inserted of course the signal is zero volt.
Now i insert only 1 I/O board (the master CPU board not inserted). The buffer are by default set in receive. So only the receiver is present on the bus.
In such situation the signal has an small offset (around 100mV)
As long as i insert further I/O Board, the offset increases.
With backplane fully populated (12 I/O board) and no CPU board, the offset is around 1.2V
Can you figure out why this happens? theoretically all buffer are turned in receive, so they should not bias the bus..
Thanks in advance
Andrea
Hi Andrea,
There is always a small amount of leakage from any CMOS device, typically measured in nanoamps. It sounds like there's a large resistance that's converting that current into voltage -- possibly just a parasitic in the system.
If all devices on the bus are receivers, then the bus needs to be held at a valid level somehow - are you only using the bus-hold inputs of the device (3Ax)?