• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 18 subscribers
  • Views 430 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN74AUP1G07: What does "Supports Live Insertion" mean in the data sheet.

John Folkerts
Prodigy 10 points
Part Number: SN74AUP1G07
Other Parts Discussed in Thread: SN74LVC1G07, SN74LVC1G125, SN74LVC1G126

Hi I am trying to understand the what is meant when some data sheets indicate support for Ioff some data sheets like the subject part indicate Ioff Supports Live Insertion,Partial-Power-Down and Back-DriveProtection.

I have looked at the TI application report SCEA026 - February 2002 which lays out three levels of live insertion isolation/protection (Level 0 to 3). 

In this document they talk about:

  1. Ioff as a static statement of inputs/outputs of the device can have voltage on them when VCC=0 without causing current into the IOs.  This capability is Level 1 Isolation (Partial Power Down).
  2. Power Up 3 State Circuitry which the device remains in the high-impedance state from a power-supply voltage of 0 V to a specified voltage.  This capability is Level 2 Isolation (Hot Insertion).
  3. Precharged IOs to reduce glitching on a active bus that device is live inserted on.  This capability is Level 3 Isolation (Live Insertion).

Can you please help point me to a more recent document that describes what is claimed/meant by statements like I referenced in the subject datasheet?  If there is ot such document can you please describe what is meant by the statements and point to the particular specs that are supporting the statement?  Also if there is a selection guide that lays out which logic families support the different features would be helpful.

In my particular application I need a device that will operate correctly down to a specified voltage and then tri-state the output.  In the picture below I need the input of the 07 to not impact the signal being pulled up by VCC_A when VCC_B is transitioning between 3.3V and Gnd.

In the picture below I need the output of the 07 to represent faithfully the logic level on the input as VCC_B transitions from 3.3V to a specified voltage and then tri-states the output as VCC_B drops from the specified voltage to GND.

  • 0
    TI__Guru* 96712 points

    Hi John, and welcome to the forums!

    FYI - your pictures didn't come through. This forum is a bit finicky when posting images -- there's an FAQ on how to get them into a post here.

    The device you mentioned has partial power-down protection, but not power-up three state or precharged I/Os.  I think it's just a poor choice of words. You could take "supports live insertion" to mean that it 100% covers all requirements for live insertion, or to mean that it provides assistance for live insertion. I think the author was trying to get across the latter. Any "Level 3" device you find will also have partial power-down protection.

    As much as I'd love to update all 3700+ datasheets in my portfolio to be consistent, I'm afraid that would take me many years (although I do continually make updates!). I can tell you the best place to check for these three features to help you while I'm in the process of making my updates.

    For a device with partial power-down protection, you will find an "Ioff" specification in the Electrical Specifications table. This will tell you exactly how much leakage is allowed in that mode, and will identify the supply condition of VCC = 0V.

    For a device with power-up three state (aka PU3S), you will find a "∆t/∆VCC Power-up ramp rate" specification in the Recommended Operating Conditions. That one's a bit more subtle -- although the front page should also list "PU3S" or "Power-Up 3-State".  This spec indicates that the device will remain in high impedance from 0V supply up to a value where the OE pin will be active and can hold the outputs in high impedance. This guarantees that you won't have any glitches at the output during your power ramp.

    The last one is easy to spot (and there aren't many parts with it) by looking at the pinout of the device. A device with precharged I/O pins will hav a "BIAS VCC" pin that provides the input voltage for the precharging.

    I actually don't like that we list it as "Isolation" in any of our datasheets or app notes, since that term actually has an important meaning outside of digital logic, and it's completely different from the meaning here.

    The SN74LVC1G07 is an open-drain device, so it doesn't have a positive driver at the output. It will drive low as long as the internal circuitry is active, and will be high impedance at all other times.

    If you need a buffer with a tristate output, you could look at using the SN74LVC1G125 or SN74LVC1G126. Both of those also have Ioff and will have high-impedance outputs as long as VCC = 0V.