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SN74AVC4T774: Power sequencing and glitches

Part Number: SN74AVC4T774
Other Parts Discussed in Thread: SN74AXC4T774

Hello Team,

the SN74AVC4T774  supports Partial Power Down.

The paragraph mentions "disabling I/O outputs", I/O outputs means also "inputs".

In the following FAQ, it is mentioned clearly "Input and Outputs pins" enter in high impedance state.

But this does not reflect in the datasheet.

  • Can you confirm it for the SN74AVC4T774 if both In and Out go in high impedance?

The SN74AXC family is advertised on not having the glitches  on power up.

  • Would the SN74AVC4T774 part suffer from glitches?
  • If so, what kind of glitches should we expect and under what conditions?

Thanks,

SunSet

  • Hey Sunset,

    CMOS inputs like the ones you see with these devices are always high impedance. Since its a transceiver, the output is also an input. Disabling the 'output' will put the I/O in a high impedance state. 

    AXC (as well as our new LXC) is specifically designed to have robust power sequencing which eliminates all glitches. This is not the case for other families.

  • Thanks for the info:

    regarding point 1)

    if VCCB is un-powered, the VCCB-I/O pins can safely float?

    Regarding the glitches:

    If we hold OE disabled, no glitches will happen regardless of power up sequence?

    Thanks,

    SunSet

  • Hey SunSet,

    No the I/O are also inputs, and inputs should not be left floating. The SN74AXC4T774 device's glitch suppression circuitry acts as a weak pull-down when the device is disabled.

    The OE circuitry may not hold the I/O in a hi-z state if VCCA isn't powered so this won't be as foolproof  as the AXC families glitch suppression.

  • Hello Dylan,

    I do have some clarification/questions for which I would need your comments:

    No the I/O are also inputs, and inputs should not be left floating. The SN74AXC4T774 device's glitch suppression circuitry acts as a weak pull-down when the device is disabled.

    By device disabled, do you mean VCCB = 0V?
    I am asking if VCCA=3.3V & VCCB=0V, can B[4:1] float since these are receivers assumed to be associated with VCCB and thus unpowered?

    The OE circuitry may not hold the I/O in a hi-z state if VCCA isn't powered so this won't be as foolproof  as the AXC families glitch suppression.

    I will likely keep VCCA powered at all times. I can guarantee sequenced/controlled VCCA power up before VCCB.
    VCCB may have to be powered up/down at various times, if it disables the B-Receiver (point above).
    I can provide OE controls, i.e. guarantee it is HI during VCCB power-up or power-down if that will prevent glitches.

    Thanks,

    SunSet

  • Hey Sunset,

    If B port is floating then the high currents that could be observed would be coming from the VCCB supply. If the power supply isn't sourcing any current then this won't be an issue.

    This configuration will most likely keep the device from glitching (this is even more apparent with the prototype working in this way) since the control circuitry is always supplied and the devices will be manually disabled. However, I can only guarantee no glitches with the AXC device since there was extensive testing to do so.

  • Out of curiosity…

    The SN74AXC has Schmitt Trigger inputs. I thought with Schmitt Trigger inputs it greatly improves the issue with floating inputs (due to hysteresis).

    However in the SN74AXC, they still refer to the same app note about “Do not float inputs”.

    ??

    Thanks,

    SunSet

  • Hey Sunset,

    AXC does not have schmitt-trigger inputs, but you are correct in your thinking that they will help in this situation. With the larger hysteresis, its more likely you won't see any oscillations due to a slow or floating input. However, you can still see higher currents due to a floating input even with Schmitt-triggers (just not as much as a normal CMOS input) so its always recommended to avoid floating nodes.