What kind of effect can be expected when designing a circuit in which a capacitor (0.1uF) is directly connected to the output pin of SN74LVC1G17DCK?
There is no limiting resistor between the output pin and the capacitor.(=oohm)
1)Is there a risk of destruction by EOS(Electrical over stress)?
2)I would like to confirm how much excessive current should flow before the failure occurs at the timing of transition from High to Low or Low to High.