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SN74LVC1G17: SN74LVC1G17DCK Output Electrical specification

Part Number: SN74LVC1G17

What kind of effect can be expected when designing a circuit in which a capacitor (0.1uF) is directly connected to the output pin of SN74LVC1G17DCK?

There is no limiting resistor between the output pin and the capacitor.(=oohm)

1)Is there a risk of destruction by EOS(Electrical over stress)?

2)I would like to confirm how much excessive current should flow before the failure occurs at the timing of transition from High to Low or Low to High.

  • 1. The current is limited only by the buffer's own output impedance (about 17 Ω), and the capacitor's ESR. This will exceed the absolute maximum rating, and can indeed destroy the device.

    2. The absolute maximum rating is ±50 mA.

  • 1. OK, Thank you.

    2.How many seconds should ± 50 mA not be exceeded?

       I simulated using the PSPICE model.

       As a result, even if only 10pF is connected, it will exceed the specified value (± 50mA).

  • Hello,

    PSpice models aren't perfect - they can only show you an estimation of performance. It's unlikely that the device will exceed 50mA during switching with a 10pF load in the real world.

    We recommend to not exceed 70 pF without adding a series limiting resistor, unless the datasheet states otherwise.

  • Does a 0.1uF connection affect long-term reliability?
    In fact, would you have an idea to investigate the current value flowing?

    I want to know the impact on the mass-produced.

  • 100000 pF is larger than 70 pF. Of course this affects reliability.

    3.3 V / 50 mA = 66 Ω. But you want to stay away from the absolute maximum rating, so use something like 100 Ω in series before the capacitor.

    Why do you need such a large capacitor at the output? What is the actual problem you're trying to solve?