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Looking for a 6-ch low-skew CMOS inverter

Other Parts Discussed in Thread: CD74AC04, SN74LVC2G04-EP, SN74AHC04-EP, SN74AHCT04

Hello TI experts,

I am looking for a 6-ch CMOS inverter. My major request is lowest part-to-part skew and channel-to-channel skew, i.e. tpd is not critical as long as it is uniform from part to part. Operating temperature should satistify -55C to 125C and input voltage is 5V. Do you have any suggestion?

I checked the datasheet of CD74AC04 and it mentions that the propagation delay is 1.6ns minimum and 6.5ns maximum over temperature range -55C to 125C. What is the part-to-part skew and channel-to-channel skew at a specific temperature of this part?

Looking forward to your reply. Thanks in advance.


  • CDxxx devices were acquired from Harris Semiconductor; I doubt that TI would have more information than what is already published.

    For all TI logic devices, channel-to-channel skew is less than 1 ns. As far as I know, device-to-device skew data is usually not available, and you have to take the theoretical worst case (6.5 ns − 1.6 ns).

    In general, devices with lower propagation delay also have lower skew. But at 5 V, there is no faster six-channel alternative to the CD74AC04. The SN74AHC04-EP has the same speed, but uses a different process. The two-channel SN74LVC2G04-EP would be faster.

  • Hi Clemens,

    Thanks for your such quick reply.

    The SN74AHC04-EP is not available at Digikey, so I'm afraid I will not use the prat in my design.

    For all TI logic devices, channel-to-channel skew is less than 1 ns.

    Do 'all TI logic devices' include CDxxx devices?

    My alternative selection is SN74AHCT04. Its min and max propagation delay are 1ns and 8.5ns, respectively, which are a little worse than CD74AC04. If part-to-part skew is usually not available, I will have to caliberate each board afterwards, which is also acceptable. But the channel-to-channel skew must be lower than 0.5ns. Do you think this part satisfy this requirement?


  • Yubing,

    Yes this will include the CDxxx devices.

    Here's some more information on the skew : [FAQ] What is the difference in timing between gates in the same device? How much skew is expected within a given logic device? What is the part-to-part skew?

    We don't guarantee part-to-part skew so you'll probably need to calibrate afterwards. 
    As Clemens mentioned the skew will be ≤ 1ns typical between any channel outputs at any one temperature. Across all temperatures, you can see up to 3ns. 
    The SN74AHCT04 and the CD74AC04 are CMOS devices so typically you can expect a max skew of approximately 250ps. So accordingly, I do think you could satisfy the 0.5ns requirement but it's important to note that this is not guaranteed however. 


  • Rami,

    Thanks for your detailed explaination. I will try these two parts with SOIC-14 package which is common for TI logic devices.