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Logic

Logic

Logic forum

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Texas Instruments (TI) Logic support forum is an extensive online knowledge base where millions of technical questions and solutions are available 24/7. You can search logic IC content or ask technical support questions on everything from voltage level translation and transceivers to standard logic gates and specialty logic devices. Find the right solution for your circuit design challenges by using our TI E2E™ support forums that are supported by thousands of contributing TI experts.
Frequent questions
  • [FAQ] How do I size my external RC components surrounding Auto-Bi Directional Translators to fit my System Requirements?

    Jack Guan
    Jack Guan
    Part Number: TXB0108 TXB0102 LSF0102 LSF0101 TXS0104E LSF0108 LSF0002 TXB0104 TXB0106 TXB0101 TXS0108E TXS0101 TXS0102 LSF0204 Tool/software: Auto Bi-Directional translators demand additional design considerations over other translators, such as external…
    • 5 months ago
    • Logic
    • Logic forum
  • [FAQ]: My simulation in ICS is very slow - how do I fix it?

    Malcolm Lyn
    Malcolm Lyn
    FAQ: TPLD > Current FAQ The two biggest causes of slow simulation are: Fast oscillators and switching signals Large simulation timescales (simulations that take 1+ seconds) If the simulation is utilizing a square wave with a period that is…
    • 6 months ago
    • Logic
    • Logic forum
  • [FAQ] Are TPLDs pin-to-pin compatible with competitor devices?

    Malcolm Lyn
    Malcolm Lyn
    FAQ: TPLD > Current FAQ Numerous TPLD products are either pin to pin or layout compatible with competing products. Our products utilize standard, JEDEC packaging standards.
    • 6 months ago
    • Logic
    • Logic forum
  • [FAQ] Can my TPLD be changed after programming?

    Malcolm Lyn
    Malcolm Lyn
    FAQ: TPLD > Current FAQ Once a TPLD is permanently programmed or “burned” through OTP, the design cannot be changed. If you wish to change your design after permanently programming an OTP part, a new, previously unprogrammed part must be used.
    • 6 months ago
    • Logic
    • Logic forum
  • [FAQ] How is TPLD programmed?

    Malcolm Lyn
    Malcolm Lyn
    FAQ: TPLD > Current FAQ TPLD is programmed through SPI communication enabled by the programmer firmware and InterConnect Studio (ICS). Each TPLD device uses 5 pins to program the device: 4 pins for SPI communication and 1 pin (GPI) that provides a specific…
    • 6 months ago
    • Logic
    • Logic forum
  • [FAQ] What do I use to program TPLD?

    Malcolm Lyn
    Malcolm Lyn
    Other Parts Discussed in Thread: TPLD1201 FAQ: TPLD > Current FAQ TPLD is programmed through our software tool, InterConnect Studio (ICS) , in combination with a TPLD programmer and EVM. TPLD programmers and EVMs can be found on the “Hardware development…
    • 6 months ago
    • Logic
    • Logic forum
  • [FAQ] Can I permanently program TPLD in-system or in production myself?

    Malcolm Lyn
    Malcolm Lyn
    FAQ: TPLD > Current FAQ No, current devices do not support in-system or inline programming (support is planned for future devices). For large scale production, we recommend you have TI program the devices before shipping. Customers can program devices…
    • 6 months ago
    • Logic
    • Logic forum
  • [FAQ] Can a third party program TPLD for me?

    Malcolm Lyn
    Malcolm Lyn
    FAQ: TPLD > Current FAQ Yes. Currently TI has enabled Dediprog to work as a third party for programming TPLD.
    • 6 months ago
    • Logic
    • Logic forum
  • [FAQ] Can TI program TPLD for me?

    Malcolm Lyn
    Malcolm Lyn
    FAQ: TPLD > Current FAQ Customers can order devices for production through InterConnect Studio (ICS). TI can program devices (at no additional cost!) before shipping with the submitted design if the order quantity is one reel or more (3000 units). …
    • 6 months ago
    • Logic
    • Logic forum
  • [FAQ] Does TPLD have memory? What kind of memory does TPLD use?

    Malcolm Lyn
    Malcolm Lyn
    FAQ: TPLD > Current FAQ TPLD uses Floating-Gate One-Time Programmable (OTP) technology to program its parts, as opposed to other Non-Volatile Memory techniques such as eFuses or AntiFuses, or Volatile Memory technologies such as EEPROM or RAM. Floating…
    • 6 months ago
    • Logic
    • Logic forum
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View FAQ threads
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  • Answered

    LSF0108-Q1: The high level output voltage of A side is clamped by VrefA 0 Locked

    693 views
    10 replies
    Latest over 2 years ago
    by chaodong deng
  • Answered

    SN74HCS04: Hysteresis variation with temperature and supply voltage 0 Locked

    518 views
    4 replies
    Latest over 2 years ago
    by Emrys Maier
  • Answered

    TXS0108E: solution support GPIO and I2C without external pull-up 0 Locked

    700 views
    7 replies
    Latest over 2 years ago
    by Clemens Ladisch
  • Answered

    SN74LVC1G07: High-level input voltage with VCC between 3.6 and 4.5 V 0 Locked

    500 views
    3 replies
    Latest over 2 years ago
    by user4497266
  • Answered

    SN74LVC2G08: When have expanded operating temperature range? 0 Locked

    319 views
    2 replies
    Latest over 2 years ago
    by Daisuke Higa
  • Suggested Answer

    SN74HC165: Timing requirement between CLK and /LN 0 Locked

    508 views
    1 reply
    Latest over 2 years ago
    by Emrys Maier
  • Not Answered

    [FAQ] SN74HCS00: The Logic Industry's Smallest Leaded Package; DYY 0 Locked

    3730 views
    0 replies
    Started over 2 years ago
    by Brandt Burgdorf
  • Suggested Answer

    PLC signal at 12V to 5V TTL 0 Locked

    963 views
    2 replies
    Latest over 2 years ago
    by Michael Ikwuyum
  • Suggested Answer

    LSF0108-Q1: The output voltage of A side is limited by VrefA 0 Locked

    712 views
    4 replies
    Latest over 2 years ago
    by Michael Ikwuyum
  • Suggested Answer

    TXS0104E: Output lowlever have a 0.5V electrical level 0 Locked

    281 views
    1 reply
    Latest over 2 years ago
    by Clemens Ladisch
  • Suggested Answer

    LSF0204: Qual-SPI solution for the LSF0204 0 Locked

    499 views
    3 replies
    Latest over 2 years ago
    by Clemens Ladisch
  • Answered

    SN74HC14: Pin width of SN74HC14PWR 0 Locked

    376 views
    2 replies
    Latest over 2 years ago
    by Daisuke Higa
  • Suggested Answer

    SN74LVC2G125: Dual Bus Buffer Gate With 3-State Outputs 0 Locked

    899 views
    5 replies
    Latest over 2 years ago
    by Clemens Ladisch
  • Suggested Answer

    LSF0204: Level translator 0 Locked

    497 views
    1 reply
    Latest over 2 years ago
    by Jack Guan
  • Suggested Answer

    SN74LV1T125DCKR - Regulations 0 Locked

    267 views
    1 reply
    Latest over 2 years ago
    by Owen Westfall
  • Answered

    SN74LVC1G125: SN74LVC1G125DSFR Package Type issue 0 Locked

    302 views
    1 reply
    Latest over 2 years ago
    by Owen Westfall
  • Suggested Answer

    CD4043B: input Logic level over complete temperature range? 0 Locked

    488 views
    1 reply
    Latest over 2 years ago
    by Clemens Ladisch
  • Suggested Answer

    CD40106B: Internal ESD configuration 0 Locked

    414 views
    1 reply
    Latest over 2 years ago
    by Clemens Ladisch
  • Answered

    SN74LVC1G125: SN74LVC1G125DSFR about package size 0 Locked

    394 views
    3 replies
    Latest over 2 years ago
    by Clemens Ladisch
  • Suggested Answer

    LSF0102: LSF0102 VS TXS0102 0 Locked

    462 views
    1 reply
    Latest over 2 years ago
    by Clemens Ladisch
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