https://e2e.ti.com/support/logic-group/logic/Products covered in this section are Gates, Little Logic, and Speciality Logic. To post a question click New Post.en-USTelligent Community 13https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1672494/sn74lvc2g04-sn74lvc2g04dckr---top-marking-s-o-581830/6450545Fri, 14 Aug 2026 00:55:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1b435e8d-37e2-4ee9-aa13-028b64b6bbe2Kent LiewHi Clemens, Thanks for your update. Please review the comments from my customer in below and do advise. As per customer: Our intended to purchase part is SN74LVC2G04DCKR, but the actual part in the reel is SN74AUP2G04. I did not find anywhere stated inside datasheet that both this MPN part is the same. If yes, please show / share. Thanks. Rigards, Kenthttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1672867/sn74lvc07a-confirming-the-application-design-of-the-sn74lvc07a/6450533Fri, 14 Aug 2026 00:22:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:012b353b-b1ff-4e2b-b538-3136d5c36ecaNicholas ShihHi Kollin, Thanks so much for your prompt reply and reminder. I really appreciate your timely response. Regards, Nicholashttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1672931/sn74lv165a-is-the-design-schematic-for-sn74lv165-correct/6450532Fri, 14 Aug 2026 00:21:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3f57201e-b348-4c77-9973-b5ec3f80b789Nicholas ShihHi Kollin, Thanks for getting back to me so quickly. I appreciate your prompt response. Regards, Nicholashttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1673183/sn74aup1g07-operating-in-ambient-temperature-higher-than-what-s-specified-in-recommended-operating-conditionsThu, 13 Aug 2026 22:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ff7794e0-f6dd-47c9-ac47-46912d44ebd0Landon MyersPart Number: SN74AUP1G07 Per the FAQ, TJmax for SN74AUP1G07 is 150°C. We've been told that if "the device is operated at its maximum datasheet ratings for ambient temperature and output power, the junction temperature will likely still be far below the maximum allowable value." However, the datasheet only lists a recommended operating free-air temperature of -40°C to +85°C, not a maximum. Does this mean that the device can be operated above that range, provided that the junction temperature does not exceed the maximum of +150°C? Example: Let's say I use the thermal resistances provided in the datasheet to model the component in my FEA software, and calculate the resulting junction temperature based on the power dissipated within the component. As long as the junction temp is below 150°C, does it matter what the ambient temperature is?SN74AUP1G07https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1672931/sn74lv165a-is-the-design-schematic-for-sn74lv165-correct/6450060Thu, 13 Aug 2026 16:17:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e6c7f920-2a81-4d7d-b922-ed50f256e579Kollin EwingHi Nicholas, The schematic looks correct. Nothing needs to be added or modified. Regards, Kollin Ewinghttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1672915/sn74ahc1g09-top-marking/6450051Thu, 13 Aug 2026 16:08:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e2f3ef54-7aa3-436f-b4d9-3450a322fd05Kollin EwingHi Alan, The top markings show what FAB the device was manufactured in. Some devices tend to have stronger slew rates depending on the FAB, and drive strength can differ batch to batch with a stronger drive strength outputting a stronger slew rate. Regards, Kollin Ewinghttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1672896/cd74hc4514-le-upper-bar/6449998Thu, 13 Aug 2026 15:35:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:83c6309d-08a5-4e69-92a0-f9093f7ddfdeKollin EwingHi Komal, Clemens is correct. Regards, Kollin Ewinghttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1673042/txs0102-q1-partial-power-down-on-b-side/6449993Thu, 13 Aug 2026 15:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:08481444-b34a-45d9-8512-b5613e7a2657Clemens LadischIt is allowed for one supply to be disabled; in that case, all I/Os will be disabled. The TXS has internal pull-up resistors (when enabled), so you can remove R512/R513.https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1672896/cd74hc4514-le-upper-bar/6449986Thu, 13 Aug 2026 15:31:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:79e41862-b183-4b56-8320-a31e58856a39Clemens LadischYes, LE is active high and must not have a bar. The bar in the datasheet is wrong.https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1672867/sn74lvc07a-confirming-the-application-design-of-the-sn74lvc07a/6449965Thu, 13 Aug 2026 15:23:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9c89707e-4a90-499c-b389-27ec7ae2db5bKollin EwingHi Nicholas, I don't see anything that would be a cause for concern with the diagrams provided. As for connecting to the SN74LV165A, they can connect with no issues as long as you keep an eye on the continuous output current which is rated at a max of 50mA. Thank you, Kollin Ewinghttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1665580/sn74ahc1g02-q1-issue-with-sn74ahc1g02qdckrq1-cross-coupled-power-on-behavior-request-for-guidance/6449964Thu, 13 Aug 2026 15:23:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2ca47f5e-5ac8-461b-8836-a6fb45832b40Clemens LadischYes; small manufacturing variations can be amplified to make the latch start up in either state.https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1673005/txb0604-txb0604rgy-missing-package-drawing-and-example-board-layout-in-datasheet/6449908Thu, 13 Aug 2026 14:45:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:19e505ec-d968-4241-84a8-40d43edebe86Jack GuanHi Bruce, You may see this similar product with RGY mechanical information: https://www.ti.com/lit/ds/symlink/sn74auc14.pdf?ts=1786632195709&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FSN74AUC14%252Fpart-details%252FSN74AUC14RGYR Regards, Jackhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1670947/mspm0g3519-migration-from-tms570ls43x-osek-based-firmware-to-mspm0g3519-q1/6449833Thu, 13 Aug 2026 14:03:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2ab097ed-029e-41e4-9610-4cc04cb65237Diego Abad SajaminHi Sheha, 1. I am not familiar with the existing TMS570 code or the approach used here. However, if the pseudocode or overall structure can be preserved and the MSPM0 has sufficient resources to meet the requirements of the previous Hercules device, it should be possible to reuse at least some of the code. 2. I do not have enough experience with HAL/driver layers to provide detailed guidance. I recommend reviewing the TI MSP MCAL package and evaluating with your team whether it could assist in this effort. Please note that the MSP MCAL package is intended for use with EB Tresos and AUTOSAR. For interrupt handling and peripheral configuration, consult the MSPM0 Technical Reference Manual and compare it with the Hercules documentation. 3. Although I am not an ARM Cortex expert, the architectures and other implementations differ, so you should consider the following areas: Core architecture – differences in intrinsic and handling of unaligned accesses. Memory model – stack size requirements and flash limitations. Safety features – the FuSa capabilities currently available on MSPM0 . Peripheral IP – refer to the MSPM0 TRM for detailed guidance. 4. I am not aware of any reference migration projects that I can share. Best Regards, Diego Abadhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1673042/txs0102-q1-partial-power-down-on-b-sideThu, 13 Aug 2026 12:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:81f1f109-91af-49dc-aa2e-bb88a33d0711Pedro MiettoPart Number: TXS0102-Q1 Other Parts Discussed in Thread: TXS0102 Hi, I'm using the TXS0102 (snipped is below) and in our application with: A side connected to FPGA side controller, 3.3V B side connected to a few peripherals, 5.0V The 5.0V supply is enabled by the same FPGA, meaning that it is a normal use case to have 5.0V turning on and off, while side A is always on. It is not a problem to have undefined states at side B while 5.0V is off. Is our design ok with respect to power sequencing? Best regards.TXS0102-Q1TXS0102Test & Measurementhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1673005/txb0604-txb0604rgy-missing-package-drawing-and-example-board-layout-in-datasheetThu, 13 Aug 2026 10:18:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9a3e94ca-ac79-40dc-b8f4-d10b9ec6bc52Bruce HsuPart Number: TXB0604 Hi I noticed that the TXB0604 datasheet does not include the RGY (VQFN-14) package drawing or example board layout / recommended land pattern information. Could you please provide the RGY package drawing PDF and the recommended PCB footprint (land pattern) for this package? Thank you for your assistance. Best regards, Bruce HsuTXB0604SN74AUC14https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1672931/sn74lv165a-is-the-design-schematic-for-sn74lv165-correctThu, 13 Aug 2026 07:13:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bfa95298-85ba-4345-b3af-3c8e3992ffbdNicholas ShihPart Number: SN74LV165A Is the design schematic for SN74LV165 correct? Are there any parts that need to be modified or added?Industrial AutomationSN74LV165Ahttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1672915/sn74ahc1g09-top-markingThu, 13 Aug 2026 06:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:fd9e53e8-6d37-4454-ad35-28de561d21c3Alan ChangPart Number: SN74AHC1G09 HI there, 1. SN74AHC1G09 has 5 different top marking. I'm asked what they means. 38QH, 3BWF, A093, A09G, A09J? 2. customer found output side has different slew rate, and cause different negative output voltage. from data sheet, Vo min is -0.5V only, 38QH over -0.5V. Top marking: 38QH Top marking: A093SN74AHC1G09Data center & enterprise computinghttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1672896/cd74hc4514-le-upper-barThu, 13 Aug 2026 05:31:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d83dd676-b77e-44ea-945d-3aae368975f7Komal GowliPart Number: CD74HC4514 Hi Team, Regarding part number CD74HC4514M96 ,in datasheet the description for LE pin function mentioned as below When Latch Enable (LE) is high the output follows changes in the inputs (see truth table). When LE is low the output is isolated from changes in the input and remains at the level (high for the 4514, low for the 4515) it had before the latches were enabled According to this LE is not an active low pin ,still I could see upper bar mentioned for LE .Is it a typo error or the LE should have a bar . If there should be a upper bar,please mention the valid reason. Thanks & regards, KomalCD74HC4514https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1672544/txu0202-lead-finish-composition-of-txu0202dcur/6449255Thu, 13 Aug 2026 04:25:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c2d58424-14a4-4006-aa31-e10295bffa37Jack GuanHi Kota, We are still looking into this and will follow up soon. Regards, Jackhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1672692/txs0108e-txs-level-translator-used-for-ddc-lines-of-hdmi-causing-issue/6449248Thu, 13 Aug 2026 04:17:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:577b35ca-5fe6-4345-a5ff-b8b6af277be2Irfan ShaikhHi Jack, There is no external pull ups provided though. VCCA is 1.8V for TXS0108. Also, I am unable to attach the wave form of working and non-working case which we have captured in saleae. Above is the 4K and 1080- laptop captured images. The VCCA of the TXS0108E is 1.8 V , while VCCB is 3.3 V . The DDC path is: HDMI source → TXS0102DCUR → PI3WVR14412Q2ZLCEX → TXS0108ERGYR → FPGA. We observed that a 4K laptop detects the HDMI sink, whereas a 1080p laptop does not. We have measured the DC HIGH levels as approximately 5 V on the HDMI side, 3.3 V on the intermediate side, and 1.8 V on the FPGA side. We will measure the VOL on both SDA and SCL at each stage during the DDC transaction , particularly during the ACK period, and provide the waveforms for comparison. Please let us know if there is a recommended way to evaluate the interaction between the TXS0102 and TXS0108E internal pull-ups in this cascaded configuration. Regards, Irfan Below is the attached Saleae captured log with analog enabled for high and low with working and non working case e2e.ti.com/.../Testing.zip