https://e2e.ti.com/support/logic-group/logic/Products covered in this section are Gates, Little Logic, and Speciality Logic. To post a question click New Post.en-USTelligent Community 13https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654799/tda2p-acd-missed-ipc-messagesFri, 12 Jun 2026 05:37:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:32eef3d7-562d-4366-892c-f120daf7c35dPartha HazarikaPart Number: TDA2P-ACD Query as below: Our implementation flow- Good case System Power up Core A15 starts and doing some CRC Validation Core A15 waits for Core M40 to request the CRC Validation status Core M40 turned ON lately (Core A15 turned ON early) and send Validation status request to A15 M40 waits to receive the response from A15 with a timeout of 500ms A15 received the request and respond back with the validation status to M40 M40 received and validation status success Bad Case System Power up Core A15 starts and doing some CRC Validation Core A15 waits for Core M40 to request the CRC Validation status Core M40 turned ON lately (Core A15 turned ON early) and send Validation status request to A15 M40 waits to receive the response from A15 with a timeout of 500ms A15 NEVER received the request and hence not responding back with the validation status to M40 M40 timed out and reports failure (defined error code) In Core A15 multiple task initialization is happening during the system boot. One of the task is Log receiver service. This task is 50 ms periodic . It sends the IPC message to all instance of Remote Log Sender to request to initialize the remote log, providing with address of the remote log buffer in the shared memory. There is no Acknowledge and IPC RX. It's regardless of the status of each instance. This task sending IPC message to the all the cores (EVE1, EVE2, M40, DSP1, DSP2). Now, We are suspecting if the Bad case (missed IPC message) arises due to IPC resource not present. May be some timing issue or the mailbox ISR implementation missed interrupt if two interrupt comes withing same time. we can discuss more as this conversation goes on.TDA2P-ACDhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654192/lsf0108-voltage-conversion/6380493Fri, 12 Jun 2026 05:31:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:063df220-eae6-4920-814e-16d8889e7b91Brian Lin (Taiwan)The LSF0108RKSR can be used with A-side and B-side I/O pull-ups both tied to 3.3 V, but do not bias it with Vref_A = Vref_B = 3.3 V. The key rule is the LSF translator biasing, Vref_B should be higher than Vref_A by 0.8 V. So LSF translators need Vref_A at least 0.8 V below Vref_B; when Vref_A = Vref_B = 3.3 V. The output clamping is around 2.3 V, which can hurt signal integrity. See Application Note : Biasing Requirements for TXS, TXB, and LSF Auto-Bidirectional Translators Thankshttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654659/sn74lvc2g126-sn74lvc2g126---pspice-model-error/6379956Thu, 11 Jun 2026 20:01:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8273ee4b-a30b-4aea-9836-88920b802c22Nikki DengelHi Josel, I see your issue. I can get the model that is on TI.com updated, but it takes a while for the updates to take effect. It is possible to add 'third party' models to PSpice for TI. I'm a Logic expert and not a PSpice expert, but take a look at [FAQ] PSPICE-FOR-TI: How do I import a 3rd-party model into PSpice for TI? to see if it is helpful. It's not convenient, but modifying the .cir file and importing it to PSpice for TI will be much faster than waiting for it to update on the TI side. Regards, Nikkihttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1653803/sn74abt244a-sn74abt244adw---input-and-output-logic-levels-with-respect-to-vcc/6379814Thu, 11 Jun 2026 18:12:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:530d87a3-4972-4a10-9c65-0d20ef0cddc9Rodney BarahonaApologies. We won't be drawing 13mA at 5V. There is no (or very little) current draw at 5V. The only time we need to sink 13mA is when it is pulled to 0.7V or lower. The current circuit acceptes 5V logic in and drives a pin at 4.5V min. So confirming that even if we change the input to 3.3V (instead of 5V), the output will not change compared to providing it a 5V input? We will be close to a 5V output and be able to provide the 4.5V min at the output? Thank you!https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654659/sn74lvc2g126-sn74lvc2g126---pspice-model-errorThu, 11 Jun 2026 16:31:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c8e24cfa-19ec-4ba5-b783-e17551258d5aJosel GoPart Number: SN74LVC2G126 Hello, I found an error in your Spice model for the SN74LVC2G126. The error results in a divide by zero error when simulating the model. Starting at line 186 of SN74LVC2G126.lib: .SUBCKT LOGIC_TRI_STATE_OUTPUT_LVC_1i_AND_Tristate_CMOS_SN74LVC2G126 IN OUT OEZ VCC VEE EROH NROH VEE TABLE {V(VCC,VEE)} = +(1.65,112.5) +(2.3,50) +(3,37.5) +(3,29.1666666666667) +(4.5,21.875) EROL NROL VEE TABLE {V(VCC,VEE)} = +(1.65,112.5) +(2.3,37.5) +(3,25) +(3,22.9166666666667) +(4.5,17.1875) There are double 'x' values of 3 in these two tables. I assume the second line entry is meant to be 3.3. I cannot make this model change using PSPICE for TI and run a simulation; as once changed, the edited model is treated like a 3rd party part and exceeeds the limititations of the free licence. Can I be provided an updated model with accompanying .libsig Regards, JoselPSPICE-FOR-TISN74LVC2G126https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654624/sn74lvc1g08-ep-what-is-the-junction-to-case-bottom-thermal-resistance-for-the-sn74lvc1g08mdckrep/6379651Thu, 11 Jun 2026 16:25:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9369eebb-b28b-4762-8d3d-9d2c9a3f6048Beverly LesserIs there a junction-to-board thermal resistance? I found the following to be similar in packaging: Part number Rjb from datasheet Part Outline Rjb Comments SN74LVC1G06DCKR 258.6 DCK005 SN74LVC1G07DCKR 258.6 DCK005 SN74LVC1G08DCKR 60.9 DCK005 Seems low. Shouldn't this be 258.6? SN74LVC1G08MDCKREP none listed DCK005 Shouldn't this be 258.6?https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654624/sn74lvc1g08-ep-what-is-the-junction-to-case-bottom-thermal-resistance-for-the-sn74lvc1g08mdckrep/6379636Thu, 11 Jun 2026 16:15:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:86e484b1-f48f-411c-8c60-cc3acbccea81Ian GrahamHi Beverly, That information is not available for this part. Best, Ianhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654631/sn74lv14a-data-request-from-flex/6379596Thu, 11 Jun 2026 15:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3dd8ae31-d556-49d5-bb5c-d4b51782d4f2Ian GrahamHi, Due to the way E2E assigns questions, I can only answer the request for the SN74LV14APW. I recommend resubmitting with other MPNs seperately. The cross for SN74LV14APW is SN74LV14APWR . It is the same device electronically, we are just moving from all of our parts to tape and reel packaging for shipping efficiency.https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654344/tmux1308-q1-tmux1308-q1-high-voltage-level-is-applied-on-data-input-of-tmux1308-when-vcc-0v-what-is-the-upper-limit-for-leakage-current/6379571Thu, 11 Jun 2026 15:42:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a38c2b3d-9c15-40c6-9d87-ed6befa42ba7Clemens LadischFor an unpowered device, see section 8.3.5.3: The TMUX13xx-Q1 circuitry can handle an input signal present without a supply voltage while minimizing power transfer from the input to output of the switch. By limiting the output voltage coupling to 400 mV the TMUX1308-Q1 and TMUX1309-Q1 help reduce the chance of conduction through any downstream ESD diodes. This contradicts the absolute maximum ratings. It says that current leaks into the output, and does not specify how much. Can your circuit tolerate that?https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654344/tmux1308-q1-tmux1308-q1-high-voltage-level-is-applied-on-data-input-of-tmux1308-when-vcc-0v-what-is-the-upper-limit-for-leakage-current/6379500Thu, 11 Jun 2026 15:08:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0cca70c7-e6e4-4d1b-9fd0-9e471b8659baHou FangxiHi Katy, From the datasheet, there is description: " the TMUX13xx-Q1 devices do not have any internal diode path to the supply pin, which eliminates the risk of damaging components connected to the supply pin, or providing unintended power to the supply rail." So no damage to chip when VCC=0V and data input is applied high level voltage and series resistor on data input path can be used to reduce leakage. Is my understanding right? Regards, Fangxihttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654631/sn74lv14a-data-request-from-flexThu, 11 Jun 2026 15:04:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c68c6b6d-a5b7-4d2f-a8fc-c501e7b0617bManikandan MPart Number: SN74LV14A Hi Team, Good day, For this Below mentioned MPN is Obsolete kindly provide the replacement MPN. SN74LV14APW For this MPN knidly provide the below details. MPN Correct orderable MPN MPN Life cycle Phase Carrier Type Orientation Part Marking MSL ULQ2003ADR For this MPN kindly provide the correct orderable MPN for below MPN MPN Correct orderable MPN ULQ2003AQDRQ1-TR Thank you,SN74LV14Ahttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654624/sn74lvc1g08-ep-what-is-the-junction-to-case-bottom-thermal-resistance-for-the-sn74lvc1g08mdckrepThu, 11 Jun 2026 14:52:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:67128a2f-1139-4b51-9918-c3bd8b389309Beverly LesserPart Number: SN74LVC1G08-EP The datasheet for SN74LVC1G08MDCKREP lists junction-to-ambient thermal resistance, but I am looking for junction-to-case. Is that information available? Thank you.SN74LVC1G08-EPhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648569/sn74lvc1g125-sn74lvc1g125dckr-3v3-shorted-to-gnd/6379463Thu, 11 Jun 2026 14:44:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:fdacc811-1047-453c-9553-6673d9facce0Nikki DengelHi Michael, This does look like a big improvement, but it's difficult for me to say whether it is enough. It looks like the inconsistency on the output waveform is due to the variation in VCC, but I don't see evidence that there is excessive output current. That's good. This input waveform is, of course, not ideal. If it can be cleaned up at all, that would help. We've got some concerning negative voltage spikes, for example. This device can handle some momentary voltage beyond the absolute maximum limits if the input current ratings are observed, but consistent operation beyond the Recommended Operating Conditions can affect long-term reliability. How many failures have you seen so far? Is it possible to do some reliability tests on this new setup? It is difficult for me to suggest additional measures that don't involve design changes. If there is a suspicion of manufacturing defects or quality concerns, you would need to start the process with Customer returns . Regards, Nikkihttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654344/tmux1308-q1-tmux1308-q1-high-voltage-level-is-applied-on-data-input-of-tmux1308-when-vcc-0v-what-is-the-upper-limit-for-leakage-current/6379453Thu, 11 Jun 2026 14:36:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:34c2dd98-6f0b-4643-a7a6-739e6d3156a9Katy WestHi Hou, Just confirming what Clemens has stated. You must make sure that the signals on the source and drain pins never exceed the voltage on VCC. So VCC needs to be powered up before any significant signals voltage is applied. Best, Katyhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654341/sn74hcs151-q1-high-voltage-level-is-applied-on-data-input-of-sn74hcs151-when-vcc-0v-what-is-the-upper-limit-for-leakage-current/6379080Thu, 11 Jun 2026 09:38:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5be4c4ca-34e8-4756-bed2-dec1eb18b8faClemens LadischAll input pins have clamping diodes to V CC ; the absolute maximum ratings forbid such voltages, and if you apply a higher voltage anyway, the resulting current into V CC can power up the device (and any other device connected to this supply), and the current can damage the device.https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654344/tmux1308-q1-tmux1308-q1-high-voltage-level-is-applied-on-data-input-of-tmux1308-when-vcc-0v-what-is-the-upper-limit-for-leakage-current/6379078Thu, 11 Jun 2026 09:37:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7353249b-f04d-4685-8637-8b316669d5deClemens LadischThe control inputs (/EN, Ax) are overvoltage tolerant; the leakage current is specified as less than 1 µA. The I/O channels have clamping diodes to V CC ; the absolute maximum ratings forbid such voltages, and if you apply a higher voltage anyway, the resulting current into V CC can power up the device (and any other device connected to this supply), and the current can damage the device.https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654192/lsf0108-voltage-conversion/6379071Thu, 11 Jun 2026 09:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d1f6f234-0513-4869-8e64-8231118c2bdaClemens LadischThe LSF is not a transducer but a passive switch. Having the same signal voltage on both sides is possible (but pointless). What are you using the LSF for in this circuit? Can one of the voltages vary? If you want to simply disconnect the two sides, use a plain switch, e.g., 2× SN74LV4066A.https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654156/txs0101-q1-txs0101-status-of-internal-pullup-during-boot-oe-disable/6379063Thu, 11 Jun 2026 09:27:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:694547ae-3149-4031-bdc9-374169360336Clemens LadischWhen OE is low, the internal pull-ups are disconnected; see [FAQ] If the OE pin is asserted to maintain Hi-Z at the IO, will it disconnect the internal pull-up resistors in TXS devices?https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654238/sn74auc07-junction-temperature/6379060Thu, 11 Jun 2026 09:25:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:719702e6-d0c2-41ea-a3cd-57cfb3fa1e6aClemens LadischIt's 150 °C; see [FAQ] What is the maximum junction temperature (TJMAX) for a device?https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1653803/sn74abt244a-sn74abt244adw---input-and-output-logic-levels-with-respect-to-vcc/6379053Thu, 11 Jun 2026 09:23:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d6ecf958-6f60-4a33-9aeb-e0d6a5ce8731Clemens LadischThe output voltage depends only on the output current. When the output sources some current, it will be about 3.3 V. If you want a voltage near 5 V, you should use a device with strong CMOS outputs like the SN74ACT244.