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<?xml-stylesheet type="text/xsl" href="https://e2e.ti.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Logic </title><link>https://e2e.ti.com/support/logic-group/logic/</link><description>Products covered in this section are Gates, Little Logic, and Speciality Logic. To post a question click New Post.</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><item><title>Forum Post: RE: SN74LVC2G126: SN74LVC2G126 - PSpice model error</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654659/sn74lvc2g126-sn74lvc2g126---pspice-model-error/6379956</link><pubDate>Thu, 11 Jun 2026 20:01:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:8273ee4b-a30b-4aea-9836-88920b802c22</guid><dc:creator>Nikki Dengel</dc:creator><description>Hi Josel, I see your issue. I can get the model that is on TI.com updated, but it takes a while for the updates to take effect. It is possible to add &amp;#39;third party&amp;#39; models to PSpice for TI. I&amp;#39;m a Logic expert and not a PSpice expert, but take a look at [FAQ] PSPICE-FOR-TI: How do I import a 3rd-party model into PSpice for TI? to see if it is helpful. It&amp;#39;s not convenient, but modifying the .cir file and importing it to PSpice for TI will be much faster than waiting for it to update on the TI side. Regards, Nikki</description></item><item><title>Forum Post: RE: SN74ABT244A: SN74ABT244ADW - Input and Output logic levels with respect to Vcc</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1653803/sn74abt244a-sn74abt244adw---input-and-output-logic-levels-with-respect-to-vcc/6379814</link><pubDate>Thu, 11 Jun 2026 18:12:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:530d87a3-4972-4a10-9c65-0d20ef0cddc9</guid><dc:creator>Rodney Barahona</dc:creator><description>Apologies. We won&amp;#39;t be drawing 13mA at 5V. There is no (or very little) current draw at 5V. The only time we need to sink 13mA is when it is pulled to 0.7V or lower. The current circuit acceptes 5V logic in and drives a pin at 4.5V min. So confirming that even if we change the input to 3.3V (instead of 5V), the output will not change compared to providing it a 5V input? We will be close to a 5V output and be able to provide the 4.5V min at the output? Thank you!</description></item><item><title>Forum Post: SN74LVC2G126: SN74LVC2G126 - PSpice model error</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654659/sn74lvc2g126-sn74lvc2g126---pspice-model-error</link><pubDate>Thu, 11 Jun 2026 16:31:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:c8e24cfa-19ec-4ba5-b783-e17551258d5a</guid><dc:creator>Josel Go</dc:creator><description>Part Number: SN74LVC2G126 Hello, I found an error in your Spice model for the SN74LVC2G126. The error results in a divide by zero error when simulating the model. Starting at line 186 of SN74LVC2G126.lib: .SUBCKT LOGIC_TRI_STATE_OUTPUT_LVC_1i_AND_Tristate_CMOS_SN74LVC2G126 IN OUT OEZ VCC VEE EROH NROH VEE TABLE {V(VCC,VEE)} = +(1.65,112.5) +(2.3,50) +(3,37.5) +(3,29.1666666666667) +(4.5,21.875) EROL NROL VEE TABLE {V(VCC,VEE)} = +(1.65,112.5) +(2.3,37.5) +(3,25) +(3,22.9166666666667) +(4.5,17.1875) There are double &amp;#39;x&amp;#39; values of 3 in these two tables. I assume the second line entry is meant to be 3.3. I cannot make this model change using PSPICE for TI and run a simulation; as once changed, the edited model is treated like a 3rd party part and exceeeds the limititations of the free licence. Can I be provided an updated model with accompanying .libsig Regards, Josel</description><category domain="https://e2e.ti.com/support/logic-group/logic/tags/PSPICE_2D00_FOR_2D00_TI">PSPICE-FOR-TI</category><category domain="https://e2e.ti.com/support/logic-group/logic/tags/SN74LVC2G126">SN74LVC2G126</category></item><item><title>Forum Post: RE: SN74LVC1G08-EP: What is the junction-to-case (bottom) thermal resistance for the SN74LVC1G08MDCKREP?</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654624/sn74lvc1g08-ep-what-is-the-junction-to-case-bottom-thermal-resistance-for-the-sn74lvc1g08mdckrep/6379651</link><pubDate>Thu, 11 Jun 2026 16:25:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:9369eebb-b28b-4762-8d3d-9d2c9a3f6048</guid><dc:creator>Beverly Lesser</dc:creator><description>Is there a junction-to-board thermal resistance? I found the following to be similar in packaging: Part number Rjb from datasheet Part Outline Rjb Comments SN74LVC1G06DCKR 258.6 DCK005 SN74LVC1G07DCKR 258.6 DCK005 SN74LVC1G08DCKR 60.9 DCK005 Seems low. Shouldn&amp;#39;t this be 258.6? SN74LVC1G08MDCKREP none listed DCK005 Shouldn&amp;#39;t this be 258.6?</description></item><item><title>Forum Post: RE: SN74LVC1G08-EP: What is the junction-to-case (bottom) thermal resistance for the SN74LVC1G08MDCKREP?</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654624/sn74lvc1g08-ep-what-is-the-junction-to-case-bottom-thermal-resistance-for-the-sn74lvc1g08mdckrep/6379636</link><pubDate>Thu, 11 Jun 2026 16:15:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:86e484b1-f48f-411c-8c60-cc3acbccea81</guid><dc:creator>Ian Graham</dc:creator><description>Hi Beverly, That information is not available for this part. Best, Ian</description></item><item><title>Forum Post: RE: SN74LV14A: Data request from Flex</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654631/sn74lv14a-data-request-from-flex/6379596</link><pubDate>Thu, 11 Jun 2026 15:54:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:3dd8ae31-d556-49d5-bb5c-d4b51782d4f2</guid><dc:creator>Ian Graham</dc:creator><description>Hi, Due to the way E2E assigns questions, I can only answer the request for the SN74LV14APW. I recommend resubmitting with other MPNs seperately. The cross for SN74LV14APW is SN74LV14APWR . It is the same device electronically, we are just moving from all of our parts to tape and reel packaging for shipping efficiency.</description></item><item><title>Forum Post: RE: TMUX1308-Q1: TMUX1308-Q1: High voltage level is applied on Data input of TMUX1308 when VCC=0V, what is the upper limit for leakage current?</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654344/tmux1308-q1-tmux1308-q1-high-voltage-level-is-applied-on-data-input-of-tmux1308-when-vcc-0v-what-is-the-upper-limit-for-leakage-current/6379571</link><pubDate>Thu, 11 Jun 2026 15:42:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:a38c2b3d-9c15-40c6-9d87-ed6befa42ba7</guid><dc:creator>Clemens Ladisch</dc:creator><description>For an unpowered device, see section 8.3.5.3: The TMUX13xx-Q1 circuitry can handle an input signal present without a supply voltage while minimizing power transfer from the input to output of the switch. By limiting the output voltage coupling to 400 mV the TMUX1308-Q1 and TMUX1309-Q1 help reduce the chance of conduction through any downstream ESD diodes. This contradicts the absolute maximum ratings. It says that current leaks into the output, and does not specify how much. Can your circuit tolerate that?</description></item><item><title>Forum Post: RE: TMUX1308-Q1: TMUX1308-Q1: High voltage level is applied on Data input of TMUX1308 when VCC=0V, what is the upper limit for leakage current?</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654344/tmux1308-q1-tmux1308-q1-high-voltage-level-is-applied-on-data-input-of-tmux1308-when-vcc-0v-what-is-the-upper-limit-for-leakage-current/6379500</link><pubDate>Thu, 11 Jun 2026 15:08:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:0cca70c7-e6e4-4d1b-9fd0-9e471b8659ba</guid><dc:creator>Hou Fangxi</dc:creator><description>Hi Katy, From the datasheet, there is description: &amp;quot; the TMUX13xx-Q1 devices do not have any internal diode path to the supply pin, which eliminates the risk of damaging components connected to the supply pin, or providing unintended power to the supply rail.&amp;quot; So no damage to chip when VCC=0V and data input is applied high level voltage and series resistor on data input path can be used to reduce leakage. Is my understanding right? Regards, Fangxi</description></item><item><title>Forum Post: SN74LV14A: Data request from Flex</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654631/sn74lv14a-data-request-from-flex</link><pubDate>Thu, 11 Jun 2026 15:04:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:c68c6b6d-a5b7-4d2f-a8fc-c501e7b0617b</guid><dc:creator>Manikandan M</dc:creator><description>Part Number: SN74LV14A Hi Team, Good day, For this Below mentioned MPN is Obsolete kindly provide the replacement MPN. SN74LV14APW For this MPN knidly provide the below details. MPN Correct orderable MPN MPN Life cycle Phase Carrier Type Orientation Part Marking MSL ULQ2003ADR For this MPN kindly provide the correct orderable MPN for below MPN MPN Correct orderable MPN ULQ2003AQDRQ1-TR Thank you,</description><category domain="https://e2e.ti.com/support/logic-group/logic/tags/SN74LV14A">SN74LV14A</category></item><item><title>Forum Post: SN74LVC1G08-EP: What is the junction-to-case (bottom) thermal resistance for the SN74LVC1G08MDCKREP?</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654624/sn74lvc1g08-ep-what-is-the-junction-to-case-bottom-thermal-resistance-for-the-sn74lvc1g08mdckrep</link><pubDate>Thu, 11 Jun 2026 14:52:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:67128a2f-1139-4b51-9918-c3bd8b389309</guid><dc:creator>Beverly Lesser</dc:creator><description>Part Number: SN74LVC1G08-EP The datasheet for SN74LVC1G08MDCKREP lists junction-to-ambient thermal resistance, but I am looking for junction-to-case. Is that information available? Thank you.</description><category domain="https://e2e.ti.com/support/logic-group/logic/tags/SN74LVC1G08_2D00_EP">SN74LVC1G08-EP</category></item><item><title>Forum Post: RE: SN74LVC1G125: SN74LVC1G125DCKR 3V3 shorted to GND</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648569/sn74lvc1g125-sn74lvc1g125dckr-3v3-shorted-to-gnd/6379463</link><pubDate>Thu, 11 Jun 2026 14:44:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:fdacc811-1047-453c-9553-6673d9facce0</guid><dc:creator>Nikki Dengel</dc:creator><description>Hi Michael, This does look like a big improvement, but it&amp;#39;s difficult for me to say whether it is enough. It looks like the inconsistency on the output waveform is due to the variation in VCC, but I don&amp;#39;t see evidence that there is excessive output current. That&amp;#39;s good. This input waveform is, of course, not ideal. If it can be cleaned up at all, that would help. We&amp;#39;ve got some concerning negative voltage spikes, for example. This device can handle some momentary voltage beyond the absolute maximum limits if the input current ratings are observed, but consistent operation beyond the Recommended Operating Conditions can affect long-term reliability. How many failures have you seen so far? Is it possible to do some reliability tests on this new setup? It is difficult for me to suggest additional measures that don&amp;#39;t involve design changes. If there is a suspicion of manufacturing defects or quality concerns, you would need to start the process with Customer returns . Regards, Nikki</description></item><item><title>Forum Post: RE: TMUX1308-Q1: TMUX1308-Q1: High voltage level is applied on Data input of TMUX1308 when VCC=0V, what is the upper limit for leakage current?</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654344/tmux1308-q1-tmux1308-q1-high-voltage-level-is-applied-on-data-input-of-tmux1308-when-vcc-0v-what-is-the-upper-limit-for-leakage-current/6379453</link><pubDate>Thu, 11 Jun 2026 14:36:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:34c2dd98-6f0b-4643-a7a6-739e6d3156a9</guid><dc:creator>Katy West</dc:creator><description>Hi Hou, Just confirming what Clemens has stated. You must make sure that the signals on the source and drain pins never exceed the voltage on VCC. So VCC needs to be powered up before any significant signals voltage is applied. Best, Katy</description></item><item><title>Forum Post: RE: SN74HCS151-Q1: High voltage level is applied on Data input of SN74HCS151 when VCC=0V, what is the upper limit for leakage current?</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654341/sn74hcs151-q1-high-voltage-level-is-applied-on-data-input-of-sn74hcs151-when-vcc-0v-what-is-the-upper-limit-for-leakage-current/6379080</link><pubDate>Thu, 11 Jun 2026 09:38:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:5be4c4ca-34e8-4756-bed2-dec1eb18b8fa</guid><dc:creator>Clemens Ladisch</dc:creator><description>All input pins have clamping diodes to V CC ; the absolute maximum ratings forbid such voltages, and if you apply a higher voltage anyway, the resulting current into V CC can power up the device (and any other device connected to this supply), and the current can damage the device.</description></item><item><title>Forum Post: RE: TMUX1308-Q1: TMUX1308-Q1: High voltage level is applied on Data input of TMUX1308 when VCC=0V, what is the upper limit for leakage current?</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654344/tmux1308-q1-tmux1308-q1-high-voltage-level-is-applied-on-data-input-of-tmux1308-when-vcc-0v-what-is-the-upper-limit-for-leakage-current/6379078</link><pubDate>Thu, 11 Jun 2026 09:37:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:7353249b-f04d-4685-8637-8b316669d5de</guid><dc:creator>Clemens Ladisch</dc:creator><description>The control inputs (/EN, Ax) are overvoltage tolerant; the leakage current is specified as less than 1 &amp;#181;A. The I/O channels have clamping diodes to V CC ; the absolute maximum ratings forbid such voltages, and if you apply a higher voltage anyway, the resulting current into V CC can power up the device (and any other device connected to this supply), and the current can damage the device.</description></item><item><title>Forum Post: RE: LSF0108: voltage conversion</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654192/lsf0108-voltage-conversion/6379071</link><pubDate>Thu, 11 Jun 2026 09:32:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:d1f6f234-0513-4869-8e64-8231118c2bda</guid><dc:creator>Clemens Ladisch</dc:creator><description>The LSF is not a transducer but a passive switch. Having the same signal voltage on both sides is possible (but pointless). What are you using the LSF for in this circuit? Can one of the voltages vary? If you want to simply disconnect the two sides, use a plain switch, e.g., 2&amp;#215; SN74LV4066A.</description></item><item><title>Forum Post: RE: TXS0101-Q1: TXS0101 Status of Internal Pullup During Boot/OE Disable</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654156/txs0101-q1-txs0101-status-of-internal-pullup-during-boot-oe-disable/6379063</link><pubDate>Thu, 11 Jun 2026 09:27:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:694547ae-3149-4031-bdc9-374169360336</guid><dc:creator>Clemens Ladisch</dc:creator><description>When OE is low, the internal pull-ups are disconnected; see [FAQ] If the OE pin is asserted to maintain Hi-Z at the IO, will it disconnect the internal pull-up resistors in TXS devices?</description></item><item><title>Forum Post: RE: SN74AUC07: Junction Temperature</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654238/sn74auc07-junction-temperature/6379060</link><pubDate>Thu, 11 Jun 2026 09:25:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:719702e6-d0c2-41ea-a3cd-57cfb3fa1e6a</guid><dc:creator>Clemens Ladisch</dc:creator><description>It&amp;#39;s 150 &amp;#176;C; see [FAQ] What is the maximum junction temperature (TJMAX) for a device?</description></item><item><title>Forum Post: RE: SN74ABT244A: SN74ABT244ADW - Input and Output logic levels with respect to Vcc</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1653803/sn74abt244a-sn74abt244adw---input-and-output-logic-levels-with-respect-to-vcc/6379053</link><pubDate>Thu, 11 Jun 2026 09:23:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:d6ecf958-6f60-4a33-9aeb-e0d6a5ce8731</guid><dc:creator>Clemens Ladisch</dc:creator><description>The output voltage depends only on the output current. When the output sources some current, it will be about 3.3 V. If you want a voltage near 5 V, you should use a device with strong CMOS outputs like the SN74ACT244.</description></item><item><title>Forum Post: RE: SN74AUP1G125: Temperature Rating Inquiry</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1653632/sn74aup1g125-temperature-rating-inquiry/6379036</link><pubDate>Thu, 11 Jun 2026 09:15:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:007037ad-992c-4599-831a-c5d84b6b0d8d</guid><dc:creator>Clemens Ladisch</dc:creator><description>This is a low-power device with low drive strength. Assuming that you are using the maximum recommended load (0.4 mA with the worst-case V OL = 0.45 V), the junction will have a temperature of 1.8 mW &amp;#215; 504.3 &amp;#176;C/W ≈ 0.9 &amp;#176;C above ambient.</description></item><item><title>Forum Post: RE: SN74HCS151-Q1: High voltage level is applied on Data input of SN74HCS151 when VCC=0V, what is the upper limit for leakage current?</title><link>https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1654341/sn74hcs151-q1-high-voltage-level-is-applied-on-data-input-of-sn74hcs151-when-vcc-0v-what-is-the-upper-limit-for-leakage-current/6378593</link><pubDate>Thu, 11 Jun 2026 03:37:00 GMT</pubDate><guid isPermaLink="false">cb01d8b2-d089-468d-babb-77d1d8683490:d1869845-0005-4908-ae9c-edd251a0b13f</guid><dc:creator>Hou Fangxi</dc:creator><description>In normal work condition, VCC=5V. high voltage level is applied on data input pin, the level is larger than 6V.</description></item></channel></rss>