https://e2e.ti.com/support/logic-group/logic/Products covered in this section are Gates, Little Logic, and Speciality Logic. To post a question click New Post.en-USTelligent Community 11https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1038653/sn74lv123a-is-it-ok-to-input-voltage-higher-than-the-vcc/3840578#3840578Wed, 22 Sep 2021 18:52:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:38ad716e-1899-47c3-8304-66b060bdb158Emrys Maier Hello Fukui-san, [quote userid="448113" url="~/support/logic-group/logic/f/logic-forum/1038653/sn74lv123a-is-it-ok-to-input-voltage-higher-than-the-vcc"]The recommended operating conditions only state high level input voltage as "Vih = VCC x 0.7 V (min)", but there are no max value listed.[/quote] The recommended input voltage limits are specified separately from the input high state definition: [quote userid="448113" url="~/support/logic-group/logic/f/logic-forum/1038653/sn74lv123a-is-it-ok-to-input-voltage-higher-than-the-vcc"]Is it OK to apply a input voltage larger than VCC? Or are there any max condition of Vih?[/quote] Yes, the input voltage can be up to 5.5V, independent of V CC . V IH is only an indicator of the "high" input state -- so long as your input voltage is above the minimum value (0.7*Vcc), the device will detect that as a 'high' input. https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1038653/sn74lv123a-is-it-ok-to-input-voltage-higher-than-the-vccWed, 22 Sep 2021 17:59:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:97abecae-8751-452a-bc73-1fc8ff897be9Ryotaro Fukui Part Number: SN74LV123A Hello team, I received a question from my customer about behavior of monostable multivibrator logic "SN74LV123A". Customers are willing to use VCC = 3.3V, and input voltage Vi = 5V(typ) for their application. Vcc(3.3V) < Vi(typ 5V) < 5.5V Is it OK to apply a input voltage larger than VCC? Or are there any max condition of Vih? The recommended operating conditions only state high level input voltage as "Vih = VCC x 0.7 V (min)", but there are no max value listed. Best Regards, Ryotaro Fukui SN74LV123Ahttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1038263/cd74ac164-schematic-example/3840453#3840453Wed, 22 Sep 2021 17:36:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b907eaf1-3939-4007-a723-468b0c8bddf2Emrys Maier Hi Hardy, Thanks for pointing out the error in the datasheet that the pin counts are wrong. You are correct that those should say "14-Pin" on both packages. I will put this in our errata list to fix in the next datasheet update. The values of R1 and C1 will depend on the customer's system requirements. What is their voltage supply ramp rate? Do they have a limitation on the startup time allowable for the shift register? To give you a reasonable estimate of the values required, I hope this inequality helps: dVcc/dt := power up ramp rate, in volts per second t_startup := maximum startup time allowable, in seconds This isn't precise, but it should give a reasonable estimate of the values required. - For example, if the power up ramp rate is 1us/V and the maximum startup time were 100us, then the range of values for tau would be: 500ns < tau < 100us In this case, a 10k resistor and 1nF capacitor would work. Once a prototype system is built, these values could be adjusted to optimize operation. https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1038263/cd74ac164-schematic-example/3840442#3840442Wed, 22 Sep 2021 17:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4fa2d1c3-a8bd-48fd-9eae-fee6db422818Clemens Ladisch These packages do have 14 pins. The pin count below the image is an octal number wrong. The RC circuit must be slow enough so that the /CLR input is still low when V CC has reached the minimum supply voltage. So this depends on how fast V CC powers up. https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1038263/cd74ac164-schematic-example/3840396#3840396Wed, 22 Sep 2021 16:59:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:fe6632af-5c6d-45d2-b8bf-c064c084b045Hardy Xue Hi Dylan, Thanks for your reply. There are 2 questions for SN74HCS164 as below: 1. Why package show 16-pin? The actual pinout only 14 pins. 2. What is the RC filter value is recommended? Best regards, Hardy https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1032261/sn74avcb164245-output-voltage-characteristics-voh-vol/3840170#3840170Wed, 22 Sep 2021 14:41:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2400c7a4-c463-4b6b-b621-e8635117e31bDylan Hubbard Hey Shiga, I'm happy this was helpful, I recommend bookmarking our FAQ page as its a great resource for any question regarding Logic or Voltage translation. It would also help if you marked this as resolved so others that may have the same question see an approved answer they can refer to. https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1036683/sn74lvc1g125-sn74lvc1g125-6-dbvr/3840132#3840132Wed, 22 Sep 2021 14:23:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:daefaf7f-c63b-437d-934e-84b290665cf7Emrys Maier[quote userid="414488" url="~/support/logic-group/logic/f/logic-forum/1036683/sn74lvc1g125-sn74lvc1g125-6-dbvr/3839931#3839931"]Because the rising edge of the input signal is slow, if a comparator is used, when the voltage is near the middle voltage, will the power consumption of the comparator (even increases), but still much smaller than SN74LVC1G125?[/quote] You may want to ask your question to the comparators team rather than the logic team (ie post a question with a comparator part #). My understanding of a comparator is that it uses a constant current source for the differential amplifier input, which means that the input voltage won't affect the supply current. I expect that most comparators will have much lower current consumption than the SN74LVC1G125 if the input signal is held between VIH and VIL. [quote userid="414488" url="~/support/logic-group/logic/f/logic-forum/1036683/sn74lvc1g125-sn74lvc1g125-6-dbvr/3839931#3839931"]And the output of the comparator can also be kept stable, is this understanding right?[/quote] I expect that will depend on the input signal - if it has any noise and the input is right at the threshold, I would assume that the output would change with the input noise. Probably another good question for the comparators team. [quote userid="414488" url="~/support/logic-group/logic/f/logic-forum/1036683/sn74lvc1g125-sn74lvc1g125-6-dbvr/3839931#3839931"]In addition, if the comparator is designed as a hysteresis comparator, will the power consumption be smaller and the output will be more stable? (At mid-level voltage)[/quote] Compared to the LVC (standard CMOS input) device? Definitely. Compared to a Schmitt-trigger input device like SN74HCS125 -- it will probably depend on which comparator you select. The input voltage vs current is provided in the HCS datasheet: With a 3.3V supply, the supply current can be as high as 100uA for the HCS device. If you note that the peak current from Clemens's reply above shows ~4mA peak for the standard CMOS device, there's quite a difference. https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1037807/txs0102-txs0102/3840112#3840112Wed, 22 Sep 2021 14:13:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5e5db201-fb1f-4396-a7db-f94aa4e4af6fDylan Hubbard Hey Adrian, To verify if its the device is damaged or if the problem lies with the interfacing devices, this will be the best way. https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1036126/sn74hc125-voh-for-3-3vcc/3840110#3840110Wed, 22 Sep 2021 14:12:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:34de19f7-9cf6-476a-9a15-add724d8c728Denny Huang Hi Clements The customer only reworked U3118.8 as floating manually, other pins of this device are still mounted on PCB and they are not floated. The customer are not sure if it has high impedance against VCC and GND since we didn’t disable output that OE#1-4 are connected to GND as enabled always. Many thanks Denny https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1032261/sn74avcb164245-output-voltage-characteristics-voh-vol/3840101#3840101Wed, 22 Sep 2021 14:11:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d656c3e2-423f-47d0-bdf1-7f24c085486aShiga Yuichi Hi Dylan, Thank you for your information. It helps me a lot, and solve my qustion. https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1038384/txs0102-ibis-model-detail-required/3840080#3840080Wed, 22 Sep 2021 14:01:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:92166b9d-9ac9-4890-9a6f-2be3b3315d5dDylan Hubbard Hi Ayush, This device doesn't use the typical buffered architecture that IBIS simulates the signal integrity for. Due to that, it doesn't have an IBIS model. https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1038541/sn74ahct125-ta-of-sn74ahct125pw/3840078#3840078Wed, 22 Sep 2021 14:00:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:710da621-d1f6-4309-a90b-51f19ea7aa4aEmrys Maier Hi Wendy, The front page orderables table is often out of date in our older datasheets. The Package Option Addendum has the latest and most accurate information. In this case, the PW package supports up to 125C. I'll mark this as an error that needs to be fixed when we update this datasheet to the new standards. https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1038381/sn74avc4t245-ibis-model-detail-required/3840073#3840073Wed, 22 Sep 2021 13:59:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6f3cd89c-57cd-4ee8-ac20-91475f1edd76Dylan Hubbard Hi Ayush, What details are you looking for? https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1038462/sn74lvc2g07-out-of-input-transition-rise-rate/3840072#3840072Wed, 22 Sep 2021 13:58:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5b882bf1-6545-442d-ba11-b3c2daa9d486Emrys Maier Hello, The issues with slow inputs are explained in this FAQ: How does a slow or floating input affect a CMOS device? The short answer is - yes, this presents a risk of reduction in reliabilty and possibly oscillatory outputs. Typically with an open-drain device, the oscillations at the output are not visible because the output transitions are so slow. In this case, the only issue is reduction in reliability. We don't have any data that shows how much this will affect reliability, so I don't have any way to predict a failure rate or time. [quote userid="262575" url="~/support/logic-group/logic/f/logic-forum/1038462/sn74lvc2g07-out-of-input-transition-rise-rate"] the input signal is 33.6us/1.2V = 28000ns/V.[/quote] Before I present solutions -- can you verify if they are operating the device at 1.2V? The LVC family only supports 1.65V to 5.5V operation. Do we have a schematic and/or scope shots of operation? https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1038406/sn74ahc240-input-signal-beyond-min-abs-max-for-1ns/3840056#3840056Wed, 22 Sep 2021 13:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:cbf4c878-6cce-42ac-b300-d50bcc6cc9dbEmrys Maier We treat the maximum rating as absolute - ie you should never exceed 20mA, for any length of time. I agree that the wording in the datasheet is not great. I do understand that short pulses carry very little energy, which is how our devices can survive ESD strikes of 2000 V -- however we do not rate logic device clamp diodes for transient events based on energy -- if a customer wants to count on this not being an issue, it would be up to them to take on that risk. I would recommend to avoid getting anywhere near the abs max values. If a system is operating a logic device at the abs max limit, then the design should be updated to avoid that. What is being asked is different from that subject -- ie the question is about input voltage, not input current. Most likely, the customer hasn't measured input current and only has seen a voltage waveform. With only 1ns of time below -0.5V, it is extremely unlikely that the diode has had time to reach 20mA of current. Quite often, it takes a few nanoseconds for the diode to even start conducting at all. If this is a concern for the customer, a series resistor can be added to prevent the current from ever reaching 20mA -- only 10 ohms is required with such a small overshoot. - To be clear - if this device were to fail, and that failure came across my desk, I would point out the overshoot as a possible cause. Adding a resistor is cheap and effective for preventing issues from this type of issue. https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1038034/sn74lvc1g07-product-oxidation-on-the-legs/3840037#3840037Wed, 22 Sep 2021 13:35:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7caeb181-8602-4e61-95a5-79047c511e15Emrys Maier No, I asked if you had some type of issues with using them. I also suggested starting an FA if you believe this to be an issue. https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1038377/lsf0204-ibis-model-detail-required/3840036#3840036Wed, 22 Sep 2021 13:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ffb53acc-3003-43ef-8fbf-6fe89cd98f73Emrys Maier Hello, This is a passive voltage translator, so I would highly discourage you from using an IBIS simulation as your primary method of determining signal integrity. I have found that IBIS simulation is very problematic for this type of device with many simulators having unreliable results. Prototyping is the best approach for analysis of signal integrity with LSF translators. That being said, there are IBIS models for LSF family devices still available. The LSF0108 has the same channel architecture as the LSF0204 - just the bias circuitry is different. https://www.ti.com/product/LSF0108?keyMatch=LSF0108&tisearch=search-everything&usecase=GPN#design-development https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1038541/sn74ahct125-ta-of-sn74ahct125pwWed, 22 Sep 2021 12:13:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:02a391e0-d96b-414e-bb32-e6fcd0fac1bdWendy Wang1 Part Number: SN74AHCT125 Hi team, Is the TA of SN74AHCT125PW -40~125 or -40~85? It seems there is a confusion in the datasheet. e2e.ti.com/.../sn74ahct125.pdf Thanks & best regards, Wendy SN74AHCT125https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1036683/sn74lvc1g125-sn74lvc1g125-6-dbvr/3839931#3839931Wed, 22 Sep 2021 11:31:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7bc021f1-6a14-437d-8e99-fdb58f9965f0Wendy Wang1 Hi Dylan, Because the rising edge of the input signal is slow, if a comparator is used, when the voltage is near the middle voltage, will the power consumption of the comparator (even increases), but still much smaller than SN74LVC1G125? And the output of the comparator can also be kept stable, is this understanding right? In addition, if the comparator is designed as a hysteresis comparator, will the power consumption be smaller and the output will be more stable? (At mid-level voltage) Thanks! Best regards, Wendy https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1038462/sn74lvc2g07-out-of-input-transition-rise-rateWed, 22 Sep 2021 08:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5ea2047b-bec4-4899-8ab1-084c5a137177user4979989 Part Number: SN74LVC2G07 Hi sir, My customer is using SN74LVC2G07DCKR, the input signal is 33.6us/1.2V = 28000ns/V. This is out of our datasheet recommendation (max 10ns/V), will it produce any potential risk? If there will be potential risk, do we have other part without the timing requirement and pin to pin with SN74LVC2G07DCKR? Thank you. sn74lvc2g07