https://e2e.ti.com/support/logic-group/logic/Products covered in this section are Gates, Little Logic, and Speciality Logic. To post a question click New Post.en-USTelligent Community 13https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1659940/sn74avc4t245-sn74avc4t245pwr-unpredictable-consumption-on-sleep-mode/6403271Thu, 02 Jul 2026 16:22:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3f4dfdd3-058f-4c49-9fd0-56d7986fd9ebClemens LadischYou must pin all eight I/Os on both sides.https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1660607/sn74axc4t774-sn74axc4t774-oe-pin-is-tied-to-gnd-directly/6403268Thu, 02 Jul 2026 16:21:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:535fbcdc-026a-43bf-b85d-350b00c7e6d9Clemens LadischThe /OE input is not a data I/O. The datasheet says: To put the level shifter I/Os in the high-impedance state during power up or power down, tie the /OE pin to V CCA through a pullup resistor. If you do not care about the state of the I/Os during power up or power down, then you can tie /OE directly to GND.https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1660561/sn74hc42-sn74hc42-problem/6403185Thu, 02 Jul 2026 15:31:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b6b113e1-39ad-4198-89b9-ee6d61f36a37Nikki DengelHi Massimo, I do not see cause for concern. The appearance of the pins is due to 'roughened lead frame' which is intentional because it provides better solder adhesion. [FAQ] Why do the leadframes look strongly oxidized or corroded? The difference in logo is normal. Regards, Nikkihttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1660523/sn74ahct1g126-oe-pin-tied-to-vcc/6403148Thu, 02 Jul 2026 15:09:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4f5e1092-17e6-4a4f-971a-d2df6d4d95e4Chris PuiHi Gabriele, If OE is tied to VCC, the buffer will be active at all times and pass any signals that arrive on the A input. During startup, it may be the case that whatever SPI controller you are using will drive some signals to the chip select as it powers on. These signals will be passed through the buffer if OE is always high. If this is not an issue, then there should be no problem with setting OE to VCC. Best, Chris Puihttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1659940/sn74avc4t245-sn74avc4t245pwr-unpredictable-consumption-on-sleep-mode/6402957Thu, 02 Jul 2026 12:39:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e711a185-05a4-4d94-94c6-8339cd41d1cbGabriel CubasThank you so much for your help, Joshua. I'm trying to work with the transciever that's already designated for the project. If I can't get the consumption to lower to a safe level, I'll be exploring the TXU products. Regards, Gabrielhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1659940/sn74avc4t245-sn74avc4t245pwr-unpredictable-consumption-on-sleep-mode/6402954Thu, 02 Jul 2026 12:38:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b6f8c8c8-da96-4744-993e-260b6f495790Gabriel CubasGood morning, Clemens. Thank you so much for your reply. It was very helpful and elucidative. I pinned both UART TX and RX and the Airplane mode pin, wich is also interfaced by the bus transciever, with pull-up and pull-down resistors (by firmware, on the STM side - The modem side is still floating). The consumption dropped from 1,2 mA to 550 uA, wich is a great improvement. I have two more questions about the typical application: 1) Should I pin both sides of the transciever with pull up/down resistors, or pinning only one side is enough? 2) There is a 4th line that's not being used (NC). Should I also pin it?https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1660607/sn74axc4t774-sn74axc4t774-oe-pin-is-tied-to-gnd-directlyThu, 02 Jul 2026 09:15:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8b61ea7d-a68d-4e5b-be06-b5f769eff9b9TT_ChinPart Number: SN74AXC4T774 Hi, I would like to know whether I can tie / OE signal of SN74AXC4T774 to GND directly ? I saw the datasheet mentioned that SN74AXC4T774 has 71K ohm integrated weak pull-downs on all data I / Os . It seems to me that it should not be an issue even though /OE is tied to GND before VCCA/B are stable, does it make sense?SN74AXC4T774https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1660561/sn74hc42-sn74hc42-problemThu, 02 Jul 2026 07:39:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1128ef5c-df8d-4358-8bd3-22f784d27a08Alessandro FarinellaPart Number: SN74HC42 I'm Massimo Gazzato of GELSE SRL from Italy We purchased 5000 pz SN74HC42DR pin in MAY ( your invoice 5853010352) and found that pins aren't metalized. Also the TEXAS SIMBOL that identifies the state of TEXAS is different. I wanted to make it's fine. I wait your answer Best regards Massimo GazzatoSN74HC42https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1658448/sn74lv8t245-input-voltage-tolerance-on-io-pins/6402579Thu, 02 Jul 2026 07:21:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2ec79682-a33b-442f-b26e-80574e7b71dfAlexis MonaciHello Joshua, OK thank you it is good news! To be complete, do you also need to change this parameter in the specification table? And if the IO in Hi-Z are 5.5V tolerant, what is the absolute maximum in this case? Best regardshttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1660173/mspm0g5187-clarification-on-generating-separate-main-and-non-main-dfu-images/6402516Thu, 02 Jul 2026 06:37:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ea563f33-7241-42eb-8428-8c4a938206d6Pengfei XieHi Ramanathan, For default .out output format, it is a format that already includes address information inside, so the NONMAIN content will be included for corresponding address region (start from 0x41c00000) in .out file. And it is not feasible to directly divide nonmain and main content based on .out format. For .txt format, you could refer the 3.5.1.5 Generate Hex Files of MSPM0 MCUs Development Guide (Rev. G) and select TI_TXT format as output format. If your project has include NONMAIN configuration, then you will see 0x41c00000 and 0x41c00100 content included in generated .txt output file, and it is nonmain content. You could manually divide this txt file into main.txt part and nonmain.txt part. TI-TXT is a simple understanding format, the binary content is just start with a @addresss and following the bytes after the address, and a "q" is required at the end of .txt file.https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1660523/sn74ahct1g126-oe-pin-tied-to-vccThu, 02 Jul 2026 06:03:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f05ecd51-e194-40c2-85b6-98c3fa24833eGabriele PellegrinelliPart Number: SN74AHCT1G126 Hello. I'll use the buffer component SN74AHCT1G126 as a voltage translator from 3.3V to 5V in my application. The signal applied to the buffer is a SPI chip select. I would like to tied OE to VCC (5V), because I don't want to use a dedicated uC pin for this signal. In the datasheet I read "To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor", so I don't know the behavior at power up/down if the OE tied to VCC. Thanks. Gabriele.SN74AHCT1G126https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1659918/txs0108e-what-happen-if-we-did-not-provide-pull-down-on-oe-line/6402457Thu, 02 Jul 2026 05:59:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4d70a888-4d49-4362-afc8-51517e1d605cJack GuanHi Sagar, We have received your inquiry and will update here in the order it is collected. Regards, Jackhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1658976/sn74hc244-as-per-the-received-pcn-no--20260608001-0-from-texas-instruments-for-the-part-number-sn74hc244n-the-change-is-data-sheet-has-been-revised-to-rev-i-by-changing/6402409Thu, 02 Jul 2026 05:21:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3d13d67b-ddaa-4776-95c7-5bfb88cffd92Keerthi GrandhiStill datasheet is not updated.https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1659187/sn74lv1t34-vcc-open-input-3-3v/6402195Thu, 02 Jul 2026 00:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5bc7df90-03d3-4b9a-94b1-da24d43527fdShuji IshiwataHi Josh-san, Jack-san, The customer is using a 47kΩ resistor at the input as a countermeasure; this limits the current and causes the 2.5V Vcc level to drop to approximately 0.5V. They would like to confirm whether there are any issues with placing a current-limiting resistor on the input terminal of the device. Best Regards, Ishiwatahttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1660367/tpsm63603e-switch-node/6401946Wed, 01 Jul 2026 20:11:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:788672c1-2073-4baa-93d4-f4946fe0df7cFrank De StasiHello The SW pin should not be connected to anything. The VLDOIN can be connected to Vout for the 5vout design. For the 12vout design, you can tie to ground or vout. Thankshttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1660422/sn74avc4t774-letter-of-volatility-requestWed, 01 Jul 2026 19:47:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:92885e58-defa-4b43-8104-427341a2ffc5Claudia R MartinezPart Number: SN74AVC4T774 Hello, I would like to request a Letter of Volatility (LOV) for part number SN74AVC4T774 to find out if this part contains volatility or non-volatility memory. I believe part number SN74AVC4T774 is the same part as 74AVC4T774RSVR-NT, right? If it has volatilie memory: - Type (e.g. SRAM, DRAM, etc.) -Size -User Modifiable (e.g. user, machine, vendor, no) -Function -Process to Sanitize or Validate If it has non-volatile memory: -Type (e.g. BBRAM, Flash, EEPROM, etc.) -Size -User Modifiable (e.g. user, machine, vendor, no) -Function -Process to Sanitize or Validate Thank you for your time in advance. Claudia R Martinez Raytheon TechnologiesSN74AVC4T774https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1660418/sn74lvc2g34-sn74lvc2g34dckr-thermal-resistance-dataWed, 01 Jul 2026 19:21:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9256fe4b-9384-4f72-8e45-de905725de01Claudia DufourPart Number: SN74LVC2G34 The SN74LVC2G34 datasheet includes the junction-to-ambient thermal resistance for the DCK package. Are there additional thermal properties available for this package? (thetaJC, thetaJB, psiJB, psiJT, etc.)SN74LVC2G34https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1659577/cd4051b-significant-device-behavioural-change-masquerading-as-a-non-issue-between-datasheet-revisions/6401844Wed, 01 Jul 2026 18:47:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:976a5a7f-3c19-49c0-97ca-86cedeafff47Nir GilgurHello George, The goal of the new die variant is to update the design while maintaining the same operation capabilities as the old one. Clearly for this case it was greatly missed, and then mostly fixed with another PCN. There is no capability to acquire older datasheet revision externally, at least not within ti.com. Other websites like you mentioned might have it, but only internally we can pull older revisions. I have checked internally and it seems like the only information about Vil characteristics is what shown in the datasheet. Since the goal of the die shrink initiative is to update the die while maintaining the same operation characteristics, there should be no changes between the datasheets. The case here is an anomaly. If there are any changes in specifications, it will be found under the revision section of the datasheet. It is not feasible from my side to provide such a list. Right now my recommendation is to operate the devices according to the information available in the current datasheet. I know this is not ideal and they should be operated same as before, but unfortunately with this device it is not the case. Another option is to use a voltage translator for the logic pins, but I don't know if it feasible from your side. Thanks, Nirhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1659918/txs0108e-what-happen-if-we-did-not-provide-pull-down-on-oe-line/6401820Wed, 01 Jul 2026 18:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2996a1f2-067a-48d2-a433-31244e16df9cSagar KumarHi, we have following condition as shown in below image- When we intiate the shutdown in host machine only AUX_3V3 is up while 1.8V and 3.3V got off. But what we observed we are seeing WAKE on B side is 1.3V while VCCB = 0.8V. As per datasheet when OE pin is GNDED since 1.8V is not available All I/O Pins are in HI-z state so PCIE_WAKE should be on 3.3V but it is on 1.3V. Can you provide the reasoning behind this?https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1660367/tpsm63603e-switch-node/6401805Wed, 01 Jul 2026 18:22:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2a4fcd67-a379-4ca0-82e6-fb36aaaa8f9cAnicia YuI am using two of these converters to output 5V and 12V. Do I need to use a cap in VLDOIN or can I just tie it to ground?