https://e2e.ti.com/support/logic-group/logic/Products covered in this section are Gates, Little Logic, and Speciality Logic. To post a question click New Post.en-USTelligent Community 13https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1647131/mspm0g5187-request-for-detailed-guidance-on-mspm0g5117-dfu-flashing-via-tinyusb/6355972Fri, 22 May 2026 11:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:406bd82b-6b90-4fa8-9501-fbaf321f38f4Sal YeHi Ram, I am OOO till next Tuesday. I'll check when I back office. My initial though is that your firmware has some issues - is this firmware works fine when you using SWD interface to flash? B.R. Salhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648569/sn74lvc1g125-sn74lvc1g125dckr-3v3-shorted-to-gndFri, 22 May 2026 10:44:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4e2683c7-55ab-4a89-88f1-4960fd4f7e1fJens De MeyPart Number: SN74LVC1G125 We have some PCBA where the SN74LVC1G125DCKR 3V3 power input got internally shorted to GND. The output has a 100R series resistor, so output current can never exceed the maximum limit of 50mA. Do we need to take care in our design to noise on 3V3 (a 100nF capacitor is installed)? Is the component sensitive to something that might cause a short between power in and GND?SN74LVC1G125Medical & healthcarehttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1647546/sn74aup2g240-junctiontemperature-details-at-70deg-ambient-temperature/6355918Fri, 22 May 2026 10:14:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f930da46-6497-4da0-9b1e-aeb29b12a631Ra KrishnaHi Ian, Can I know the max power dissipation for the SN74AUP2G240DQER. Its not mentioned anywhere in datasheet. Regards,https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648329/sn74lvc1t45-sn74lvc1t45-behaviour-when-one-vcc-is-set-close-to-gnd/6355878Fri, 22 May 2026 09:37:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:88e6a6e1-22d4-408e-a84e-170c1cab493cTobias FischerHi Clemens, we did change the SN74LVC1T45 from one of the affected devices (all from newer production date) with the SN74LVC1T45 from an older device, which is working. Exchanging the component did help and solved the issue. I verified on two samples so far. So the essential queszion is: What could cause the SN74LVC1T45 output to show that behaviour. Is it possible that the device gets destroyed when two outputs drive on each other? Maybe during a very short period during an update. Usually, we have pull-ups setting all Chip Selects to inactive when the Pins are High-Z but during an update there might be a state of undefined port drive states causing such a condition.https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648501/sn74ahc1g00-q1-need-some-clarification-about-a-change-on-some-partFri, 22 May 2026 09:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:959acdbc-ffac-4d5e-b6eb-099ff9d3e78aTodut Dumitru EugenPart Number: SN74AHC1G00-Q1 Could you please confirm whether the change described as "Change of lead and heat slug plating" (ZVEI-ID: SEM-PA-05) refers to the component SN74AHC1G00QDCKRQ1 ? Additionally, we would like to understand if this change represents a difference between CDAT and TIEMA , or if both CDAT and TIEMA use the same lead/heat slug plating. We noticed that this specific change is not explicitly listed in the main document description and is only referenced at the bottom under the ZVEI-ID section. Therefore, we would appreciate your clarification on its applicability and impact.SN74AHC1G00-Q1https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648329/sn74lvc1t45-sn74lvc1t45-behaviour-when-one-vcc-is-set-close-to-gnd/6355823Fri, 22 May 2026 08:59:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9b21f5ba-c98f-4da9-9d4c-884c06887ff2Clemens LadischHow exactly does it affect the SPI level? An output cannot drive higher than VCC; does it pull the line down?https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648329/sn74lvc1t45-sn74lvc1t45-behaviour-when-one-vcc-is-set-close-to-gnd/6355766Fri, 22 May 2026 08:18:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a3e597f4-c207-43c5-9742-8fef9374b0b7Tobias FischerHi Clemens, thank for your input. When setting the level shifter to inactive, we have an input voltage in Vcca of below 20mV. Hope that the remaining voltage does not cause any issues here. Usually we have just set the level shifter active for the range of miliseconds by switching Vcca to 1.8V. Just measured it and the voltage out of the inverter is fully ok. I noticed we changed the inverter setting the Vcca signal within the series from 74LVC1G04 (Nexperia) to SN74LVC1G04 (TI). I am not aware of any changes between the two components but could this might be the reason for the seen misbehavior? SPI_MISO still shows some (relative strong) drive capability and influences the level on the SPI bus in a way, that we are not able to read the MISO correctly. Do you have any further ideas?https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648261/sn54hc273-junction-to-ambient-thermal-resistance/6355753Fri, 22 May 2026 08:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5b442651-aa82-4443-bf5b-80813aadc8caBart OdjasThanks Ian. But could you confirm that this parameter has not changed between the old part SN54AHC273 (CDIP, LCCC) and the new one SN54HC273 (CDIP, LCCC)? Thanks, Barthttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648329/sn74lvc1t45-sn74lvc1t45-behaviour-when-one-vcc-is-set-close-to-gnd/6355681Fri, 22 May 2026 07:11:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c14cf04c-afb9-4891-a1b2-83ff06a56f4bClemens LadischThe A output is powered from VccA, so it should not be possible for it to drive anything. The output of D8 should be exactly 0 V (nothing is pulling it high). Can you measure it? A simpler way to implement this entire circuit would be a single SN74LVC1G125 three-state buffer (it has overvoltage-tolerant inputs).https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1647131/mspm0g5187-request-for-detailed-guidance-on-mspm0g5117-dfu-flashing-via-tinyusb/6355501Fri, 22 May 2026 05:13:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d07eeb4d-fc8d-48c1-9aa2-0ad9037f2ac5Ramanathan SHi Sal Ye, Thanks for your reply. After testing the procedure, I am facing the following issues: During the flashing process, the operation stops in the middle. For your reference, I have attached a picture. As per the instructions you shared, I followed the below DFU sequence: Entered DFU Mode Unlocked BSL Entered Sample Password Password Accepted Started Code Flash using the .bin file (128 KB) However, after sending the .bin file, the flashing process gets stuck. Please share the correct flashing procedure and guide me on how to resolve this issue. During another flashing attempt, the process again stopped in the middle. After that, when I tried to enter DFU Mode again, I started getting the error: MSPM0 core failed . Let me know how to recover from this issue. I also tried using CCS, but the same issue still persists. 3.Share the .bin file flashing procedure similar to the .txt flashing procedure you shared earlier. Also guide me on how to generate .txt or .bin files from CCS builds. Currently, CCS generates only the .out file, and I am using PowerShell commands to manually convert it. Please share the recommended conversion process and required tools/commands. MSPM0 Core Failed: Debug_upload_log FYI: e2e.ti.com/.../dfu_5F00_upload_5F00_log.txt output/*.bin: Regards Ramhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1646756/cd74hc08-request-reason-for-nrnd-and-active-replacement-mpn/6355373Fri, 22 May 2026 03:37:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:271915c4-d95c-457d-bd59-64ad03768500Albert Xu1Hi Tapendra, The main issue here is that the packages are not being manufactured anymore (PDIP package). I have given the best replacement in a 300mm package for the following devices. CD74HC08E ->SN74HC08N SN74HCT02N -> SN74HCT02DR SN74HC148N -> no 300m replacement, but other packages are active CD74ACT04E -> CD74ACT04M96 SN74HC4060DBR ->no 300m replacement, but other packages are active SN74ACT240DBR -> SN74ACT240PWRhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1646467/cd74hc4067-q1-esd-ratings/6355264Fri, 22 May 2026 01:27:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:991a4627-94b0-4b3c-8287-82e1f7c51cb4Shunsuke YamamotoHi Hunter-san, Are there any recommended ESD protection diodes to protect the input pins of CD74HC4067-Q1 for the ESD test which voltage is +/-4000V? Best regards, Shunsuke Yamamotohttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1647939/tps50601a-sp-regarding-the-pin-configuration-of-tps50601a-sp/6355000Thu, 21 May 2026 20:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ddc82100-435f-4021-87f5-acc158085dc3Andy FondawHello Urano-san, After taking a look at the pin configuration figure in the datasheet, I believe that you are correct and that it should be labeled as a top view instead of a bottom view. I have made a note of this discrepancy, and it will be included in the next revision of the device datasheet. Thanks, Andyhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648329/sn74lvc1t45-sn74lvc1t45-behaviour-when-one-vcc-is-set-close-to-gndThu, 21 May 2026 19:35:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bb45e83c-eaf3-4291-9f40-9094e3b3b9e3Tobias FischerPart Number: SN74LVC1T45 Other Parts Discussed in Thread: SN74LVC1G125 , SN74LVC1G04 Dear TI team, within one of our applications, we use the SN74LVC1T45 to do level shifting of an SPI-MISO signal from 5.5V (Slave) to 1.8V (Master). To prevent driving the bus either high or low when the CS of the peripheral, we switch the Vcca of the level shifter with the help of an inverter, that is fed by the low-active Chip Select signal, according to the picture below: We verified that during the sampling and Piloting phase with a couple of hundred devices without any issues. When CHip Select was High, the output of D8 went low. Vcca went to GND and the output A of D7 wnet High Impedance. However, it now seems this behaviour changed with later batches and the output of D7 is indeed driving pulling or pushing the SPI_MISO, even when Chip Select is inactive (High). Could this be related to the fact, that the ouput of D8 is just close to GND, maybe related to the Ioff of the Vcca input from D8? Is this approach suitable in general or do you not recommend to use the SN74LVC1T45 in this way, with its Vcca fed by another logic IC? Thank you for your support on this. BR, TobiasSN74LVC1T45SN74LVC1G125SN74LVC1G04Applianceshttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648261/sn54hc273-junction-to-ambient-thermal-resistance/6354808Thu, 21 May 2026 17:16:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4ffa7dde-39cf-42e5-9c3e-bddcd4726586Ian GrahamHi Bart, We don't typically take thermal resistance values for those packages. Best, Ianhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648290/sn74ac08-sn74ac08-slew-rate/6354782Thu, 21 May 2026 16:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:11527b6d-40ed-4730-ae96-9de90f5ddddcKatherine RosasGot it - thank you!https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648290/sn74ac08-sn74ac08-slew-rate/6354770Thu, 21 May 2026 16:47:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0127a272-9703-4ae3-9707-4aeccbdb479eIan GrahamHI Katherine, Slew rate is a system level characteristic that we can't define. It depends on the load capacitance of the user's system. Here's an FAQ with details on calculating slew rate: [FAQ] What is the output transition rate for a logic device? While we can't guarantee that the slew rates will be identical, since the electrical characteristics between the devices are the same, we can at least say that the slew rates will have the same maximum output transition time.https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648290/sn74ac08-sn74ac08-slew-rateThu, 21 May 2026 16:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:41693aa3-8d12-45af-adba-f1b4677be216Katherine RosasPart Number: SN74AC08 Hello, What is the slew rate of SN74AC08? Is there a difference between SN74AC08-EP and SN74AC08-Q1 slew rate or are they the same? Thank you!SN74AC08-EPSN74AC08-Q1SN74AC08https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648220/lsf0108-logic-level-from-1-8v-to-3-3v-switching-is-not-working-from-vref_a-1-8v-to-vref_b-3-3v/6354698Thu, 21 May 2026 16:07:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e091c187-8266-46bf-8963-ae3e045d984cSiddaiah HHi Jack, Please suggest me the external pull-up values to test the expected amplitude level . Is there any other design issues in the schematics. Regards Siddaiah Hiremathhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648277/lsf0204-lsf0204yzpr-yzp-package-indicator-dot-orientation-mismatch-vs-datasheet-specification/6354667Thu, 21 May 2026 15:53:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0f37faf9-870e-4d30-8d0d-417422c2c9d8Clemens LadischPin names and pin numbers are different. Leaded and QFN devices have one-dimensional pin numbers, but BGA devices use two-dimensional pin numbers that can be easily confused with the data I/O pin names. Also note that the package outline in the datasheet (p. 22) shows the index area from the top and the balls from the bottom; the index area is pin number A3/pin name A1.