https://e2e.ti.com/support/logic-group/logic/Products covered in this section are Gates, Little Logic, and Speciality Logic. To post a question click New Post.en-USTelligent Community 13https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1647939/tps50601a-sp-regarding-the-pin-configuration-of-tps50601a-sp/6355000Thu, 21 May 2026 20:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ddc82100-435f-4021-87f5-acc158085dc3Andy FondawHello Urano-san, After taking a look at the pin configuration figure in the datasheet, I believe that you are correct and that it should be labeled as a top view instead of a bottom view. I have made a note of this discrepancy, and it will be included in the next revision of the device datasheet. Thanks, Andyhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648329/sn74lvc1t45-sn74lvc1t45-behaviour-when-one-vcc-is-set-close-to-gndThu, 21 May 2026 19:35:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bb45e83c-eaf3-4291-9f40-9094e3b3b9e3Tobias FischerPart Number: SN74LVC1T45 Dear TI team, within one of our applications, we use the SN74LVC1T45 to do level shifting of an SPI-MISO signal from 5.5V (Slave) to 1.8V (Master). To prevent driving the bus either high or low when the CS of the peripheral, we switch the Vcca of the level shifter with the help of an inverter, that is fed by the low-active Chip Select signal, according to the picture below: We verified that during the sampling and Piloting phase with a couple of hundred devices without any issues. When CHip Select was High, the output of D8 went low. Vcca went to GND and the output A of D7 wnet High Impedance. However, it now seems this behaviour changed with later batches and the output of D7 is indeed driving pulling or pushing the SPI_MISO, even when Chip Select is inactive (High). Could this be related to the fact, that the ouput of D8 is just close to GND, maybe related to the Ioff of the Vcca input from D8? Is this approach suitable in general or do you not recommend to use the SN74LVC1T45 in this way, with its Vcca fed by another logic IC? Thank you for your support on this. BR, TobiasSN74LVC1T45Applianceshttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648261/sn54hc273-junction-to-ambient-thermal-resistance/6354808Thu, 21 May 2026 17:16:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4ffa7dde-39cf-42e5-9c3e-bddcd4726586Ian GrahamHi Bart, We don't typically take thermal resistance values for those packages. Best, Ianhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648290/sn74ac08-sn74ac08-slew-rate/6354782Thu, 21 May 2026 16:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:11527b6d-40ed-4730-ae96-9de90f5ddddcKatherine RosasGot it - thank you!https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648290/sn74ac08-sn74ac08-slew-rate/6354770Thu, 21 May 2026 16:47:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0127a272-9703-4ae3-9707-4aeccbdb479eIan GrahamHI Katherine, Slew rate is a system level characteristic that we can't define. It depends on the load capacitance of the user's system. Here's an FAQ with details on calculating slew rate: [FAQ] What is the output transition rate for a logic device? While we can't guarantee that the slew rates will be identical, since the electrical characteristics between the devices are the same, we can at least say that the slew rates will have the same maximum output transition time.https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648290/sn74ac08-sn74ac08-slew-rateThu, 21 May 2026 16:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:41693aa3-8d12-45af-adba-f1b4677be216Katherine RosasPart Number: SN74AC08 Hello, What is the slew rate of SN74AC08? Is there a difference between SN74AC08-EP and SN74AC08-Q1 slew rate or are they the same? Thank you!SN74AC08-EPSN74AC08-Q1SN74AC08https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648220/lsf0108-logic-level-from-1-8v-to-3-3v-switching-is-not-working-from-vref_a-1-8v-to-vref_b-3-3v/6354698Thu, 21 May 2026 16:07:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e091c187-8266-46bf-8963-ae3e045d984cSiddaiah HHi Jack, Please suggest me the external pull-up values to test the expected amplitude level . Is there any other design issues in the schematics. Regards Siddaiah Hiremathhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648277/lsf0204-lsf0204yzpr-yzp-package-indicator-dot-orientation-mismatch-vs-datasheet-specification/6354667Thu, 21 May 2026 15:53:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0f37faf9-870e-4d30-8d0d-417422c2c9d8Clemens LadischPin names and pin numbers are different. Leaded and QFN devices have one-dimensional pin numbers, but BGA devices use two-dimensional pin numbers that can be easily confused with the data I/O pin names. Also note that the package outline in the datasheet (p. 22) shows the index area from the top and the balls from the bottom; the index area is pin number A3/pin name A1.https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648277/lsf0204-lsf0204yzpr-yzp-package-indicator-dot-orientation-mismatch-vs-datasheet-specificationThu, 21 May 2026 15:46:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a19510fc-0a2c-41b7-8320-eb969501c665Yokesh JPart Number: LSF0204 We are using the LSF0204YZPR part in our design. As per the datasheet, the location of YZP-package indicator dot corresponds to the A3 position. However, the components that we received and assembled on the board show a different orientation. As observed in Image A, the package indicator dot is positioned at location D1. This interpretation is based on the assumption that the pin‑1 reference marking, which is present on the backside of the IC, corresponds to coordinate A1 in the package grid. Using this backside marking as the reference origin (A1), the visible indicator dot on the top side of the package appears straight opposite, aligning with D1 rather than A3 as specified in the datasheet. Based on this understanding, the part has been mounted on the board as shown in Image B. Is there any change in the YZP‑package indicator dot location that has not been documented in the datasheet revision history? Since there is a mismatch between the datasheet‑defined orientation and the physical marking on the received component. Kindly confirm the correct orientation and advise on the proper method for mounting the IC.LSF0204https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648220/lsf0108-logic-level-from-1-8v-to-3-3v-switching-is-not-working-from-vref_a-1-8v-to-vref_b-3-3v/6354622Thu, 21 May 2026 15:38:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ab76a411-b0d4-4538-be5c-dc39cd60e04eJack GuanHello, Please note that external pullups are needed at the I/Os, especially on the 3V3 side to achieve this VCC as logic high. Regards, Jackhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1645981/mspm0g3519-q1-issue-flashing-mspm0g3519-custom-pcb-using-j-link-in-ccs/6354593Thu, 21 May 2026 15:28:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f6f9baed-ab5d-4886-9dba-0ec45386f115Sal YeHi Ki, Thanks for your quick support. I am OOO right now, I will summarize a detailed flow-issues when I test this example project next week. B.R. Salhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1645981/mspm0g3519-q1-issue-flashing-mspm0g3519-custom-pcb-using-j-link-in-ccs/6354586Thu, 21 May 2026 15:25:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8c1c1ed6-1766-4312-8aa5-76139ce157ccKi[quote userid="522967" url="~/support/logic-group/logic/f/logic-forum/1645981/mspm0g3519-q1-issue-flashing-mspm0g3519-custom-pcb-using-j-link-in-ccs/6354537"]And after "debug - run - add variable (pUserInputRegs) in expression window to modify and refresh - exist - next debug" several times, I can see this issues happen.[/quote] What is the exact issue you see? So far I have not seen any issues.https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1647947/sn74lvc32a-regarding-the-overshoot-tolerance-of-the-sn74lvc-series-logic-ics/6354578Thu, 21 May 2026 15:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e1646ab6-146d-4b1b-9958-1f4dc80d38c7Ian GrahamHi Takaya, That should be fine. Any very small, incidental overshoot will likely be filtered out by the internal capacitance. If you are concerned, a resistor can be added before the input pin to limit the current to be below the input clamp current limit.https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1645981/mspm0g3519-q1-issue-flashing-mspm0g3519-custom-pcb-using-j-link-in-ccs/6354572Thu, 21 May 2026 15:22:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1000503f-68f4-448c-965c-4932d28fa373KiThe reason for the issue is I disabled optimization. When I do that, it get an error. When I set the optimization to "2", the error goes away. Any idea why this happens? You typically want to disable optimization for best debug experience.https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1645981/mspm0g3519-q1-issue-flashing-mspm0g3519-custom-pcb-using-j-link-in-ccs/6354562Thu, 21 May 2026 15:19:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3a5167e1-6513-4267-a325-13b94c448892KiActually disregard my last message. I was able to resolve the build error.https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1645981/mspm0g3519-q1-issue-flashing-mspm0g3519-custom-pcb-using-j-link-in-ccs/6354559Thu, 21 May 2026 15:16:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:af637ae2-abb6-4fbf-8c38-2816bd2db299Ki[quote userid="522967" url="~/support/logic-group/logic/f/logic-forum/1645981/mspm0g3519-q1-issue-flashing-mspm0g3519-custom-pcb-using-j-link-in-ccs/6354537"] https://dev.ti.com/tirex/explore/node?isTheia=false&node=A__APKAXW5oxCnRQWU9zNiDTw__MSPM0-SDK__a3PaaoK__LATEST&placeholder=true [/quote] I am trying to build this example. But I get this build error: Do you know why?https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1645981/mspm0g3519-q1-issue-flashing-mspm0g3519-custom-pcb-using-j-link-in-ccs/6354537Thu, 21 May 2026 15:08:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c2e96215-0885-486e-92d3-548a66c7d26fSal YeHi Ki, For the complex SDK example, it has some issues when I test. Can you try this one: https://dev.ti.com/tirex/explore/node?isTheia=false&node=A__APKAXW5oxCnRQWU9zNiDTw__MSPM0-SDK__a3PaaoK__LATEST&placeholder=true And after "debug - run - add variable (pUserInputRegs) in expression window to modify and refresh - exist - next debug" several times, I can see this issues happen. B.R. Salhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648261/sn54hc273-junction-to-ambient-thermal-resistanceThu, 21 May 2026 15:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0fe4cc8f-cef4-4ec9-8c80-e9155837a94dBart OdjasPart Number: SN54HC273 Hi, What is the Junction-to-ambient thermal resistance for SN54HC273 LCCC and CDIP packages? Thanks, BartSN54HC273https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1645981/mspm0g3519-q1-issue-flashing-mspm0g3519-custom-pcb-using-j-link-in-ccs/6354519Thu, 21 May 2026 15:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ce574449-9c03-4f8b-9196-5dc84962ec55KiHello, I tried out using CCS 20.5.1 with my MSPM0G3519 LaunchPad with my SEGGER J-Link Ultra. I connected it to the launchpad as instructed on this page: https://kb.segger.com/TI_LP-MSPM0G3519 I then imported the same gpio_toggle_output SDK example. I modified the project so that the connection type is for J-Link and the generated target config looks like: I also tweaked the project to disable optimization and to add a global variable to it. Then I tried to debug the project and it worked fine: [quote userid="689875" url="~/support/logic-group/logic/f/logic-forum/1645981/mspm0g3519-q1-issue-flashing-mspm0g3519-custom-pcb-using-j-link-in-ccs/6353719"]However, in CCS, the debug variables/watch window debugging is failing.[/quote] I don't see any issues with this whether the target is halted or running. If you have issues with the latter, make sure continuous refresh is enabled so that the debugger will periodically update the variable value. Thanks kihttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1648220/lsf0108-logic-level-from-1-8v-to-3-3v-switching-is-not-working-from-vref_a-1-8v-to-vref_b-3-3vThu, 21 May 2026 13:39:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f60a5b67-203e-4f12-94e1-1aff2a233000Siddaiah HPart Number: LSF0108 Dear Team, We are currently bringing up the initial power supplies and testing the LSF0108RKSR bidirectional buffer used in our design to convert logic levels from 1.8V to 3.3V. During testing, we are facing an issue where the logic switching from 1.8V to 3.3V is not happening as expected. We have attached our schematics for your reference. Could you please review them and share your valuable suggestions to help us resolve the logic switching issue? Thank you for your support. Regards Siddaiah HiremathLSF0108Wired networking