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SN74HC595: *** Registers Many Chained

Prodigy 70 points

Replies: 7

Views: 456

Part Number: SN74HC595

Hi,

Please assist.  I have attached circuit with many shift registers chained in a line.  Also looking to add more of them.

The circuit works, however I am concerned if this is safe and reliable to use like this and also a bit baffled as to why it works ??Shift Registers Times 6.pdf

The same clock is applied to each shift register and I am wondering if there is possibilities of it going out and other shift registers down the line gets sampled at the wrong time ?

Are there any dangers to this circuit ?

What can I do to avoid these ?

Thanks !

  • Hi Neil,
    The primary concern in a chain of shift registers is ensuring that the clocks reach the devices at about the same time.

    There is some leeway because it takes time for the devices to switch, and there's also time for the data to transfer from the output of one device to the input of the next (albeit very little time...).

    It's best to setup your clock so that you have equal length lines going to each device in the chain. If you are going to have more than ten shift registers in series, you will need a clock-fanout device to ensure that your clock is driven properly to all subsequent devices. This number can also decrease if you have fairly high capacitance lines (wide/long traces with a ground plane under them). Try to limit the total load on any one buffer to 70pF.

    The easiest way to do a clock fanout is to get an octal buffer (such as SN74HC245) and tie all the inputs together, then to your clock source. Now each of those 8 buffers will redrive the clock signal, and each one can drive up to 70pF. This can be repeated if necessary - just remember that you're trying to synchronize things, so the same number of buffer stages needs to be implemented to -all- the clock signals, and also each one should have an equal length line (that means snaking the closest clock signal lines back and forth quite a bit).


    Looking for a low voltage translator? Check out the AXC family that supports 0.7V to 3.3V translation!

    The Logic Minute training page has videos on many interesting topics that all are kept shorter than 5 minutes.

  • In reply to Emrys Maier:

    Hi Emrys,

    Thank you, that helps a lot.

    So if I understand you correctly, the circuit I attached using 6 x 8bit shift registers are pretty safe as it is ?

    Even adding another 1 or 2 should be safe as long as my PCB tracks are similar, I would not need a clock-fanout device ?.

    Also noting that my clock speed is less than 1MHz.

  • In reply to Neil Badenhorst:

    Less than 1 MHz is perfectly safe.
  • In reply to Clemens Ladisch:

    Thank you !
    So lastly can you maybe give per example for my case the difference in timing between the CLOCK and first bit and last bit of the 6bytesx8bits = 48bits case ?
  • In reply to Neil Badenhorst:

    The datasheet specifies the propagation delay (tpd from SRCLK to QH') as 17 ns typical, 40 ns in the worst case at 5 V ± 10 %.
    5 × 17 ns =  85 ns; at 1 MHz, the signal edges would be 500 ns apart.

  • In reply to Clemens Ladisch:

    Thanks. So how much less than 500ns (edges apart) would be safe to operate at ?

    Lets say I take the worst case of 40ns and add another 2 8bit shift registers (so 8 in total) and end up at delay of 40ns x 7 = 280ns. Am I correct in saying this is still way safe ?

  • In reply to Neil Badenhorst:

    Changing the offset between serial data and clock by 280 ns would still leave 220 ns , which is larger than any of the set-up and hold time requirements.

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