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According to the data sheet for the CD4015B static shift register, it is possible to daisey-chain the two 4 bit registers together and daisey-chain multiple 4015's . Are there any precautions necessary to both of these? Thanks!
As with any synchronous system, you have to think how the clock will be distributed to all the devices in the chain, taking into account the load that each devices represents and the requirement of minimizing skew between the clocks arriving to each device.
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In reply to Avi Chami1:
@Albert: I wasn't so much concerned with the clock layout, I have that nailed down. I was worried about sending the data from chip to chip . Can I run a straight wire from the data-out pin of one chip to the data-in of the next chip in the chain without having to worry about the hold time vs. propagation time? The data sheet for this chip says the hold time is zero but are they zero in the real world? I was hoping to find someone who has used this chip before and had experience daisy-chaining them together. Thank you!
In reply to Fred Paine:
Adding the propagation delay to the signal is actually helping the next FF hold time. Excesive propagation delay will adversely affect your setup time, not your hold time. Shift registers main problem is actually hold time (inside the silicon), and the solution in the cases that this happens is usually inserting a buffer between flip flops.
Fred, If the daisy chain consist of just a few devices it does not matter much but when the daisy chain gets longer proper propagation delays need to be taken into considerations. In order for a shift register to work properly, the data in the last register in the daisy chain need to be shifted out first so that it can be replaced by data in the preceding register. In order to achieve this in a very long daisy chain we need to connect the clock signal the last device in the daisy chain first and the prop delays in the path will take care of the rest.
In reply to Francis Tham:
@Francis: I am daisy chaining nine CD4015 shift registers together and I am never going to clock faster than 500 khz. Do you think propagation delay will be a problem with this many chips and this clock frequency. I am using a modified H-Tree clock signal trace layout so the clock pulse is going to arrive at all nine chips within 2 or 3 nano-seconds of each other.
As long as the clock arrives to all the FFs with minimal skew, it doesn't matter wether the chain has eight or eight thousand FFs. BTW, many years ago I made chains of 6 shift register devices with eight FFs each... We used 74HC595. We didn't expect nor experienced any problems chaining them.
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