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SN74LVC1G11: SN74LVC1G11DRYR Output Behaviour while power-up

Isee
Expert 4830 points
Part Number: SN74LVC1G11
Other Parts Discussed in Thread: SN74LVC1G125

Hi,

can it be guaranteed that the output (Y) stays low while power-up (if at least 1 input is at 0V)? Or does one have to expect that the output "shifts/moves" until minimal supply voltage is reached?

Thank you,

Andreas

  • 0
    TI__Guru* 96591 points
    Hi Andreas,
    The SN74LVC1G11 is only guaranteed to operate correctly between 1.65 and 5.5V by the datasheet. I don't have test data for this device below 1.65V for operation.

    That being said, typically the output will remain low during power-up if the inputs are in a defined low state, however there are some cases where small glitches have been seen on some logic devices. Typically these happen right around the turn-on voltage for the FETs (~850mV) and will usually track the supply for a short time before reverting back to ~0V.

    Is your system sensitive to small glitches like this? There are some possible solutions if so -- can you share your application?
  • 0 in reply to Emrys Maier
    TI__Expert 4830 points

    Hi Emrys,

    thank you very much - in order to avoid misunderstanding, could you look at the following: 

    Application:

    -          1st and 2nd Input: signals from processor (which could rise at power-up)

    -          3rd input: RESET-Signal (which is 0V at power-up)

    -          Idea: At Power-Up the Output of the Gate should always be <0,25V (or <0,9V if we can define a max. glitch-time?)

     Can this be achieved with the SN74LVC1G11?

    Regards,

    Andreas

  • 0 in reply to Isee
    TI__Guru* 96591 points

    Hi Andreas,

    We can't guarantee operation as described with this device only, however you could add an SN74LVC1G125 to the output to guarantee a high-impedance output until desired operating voltage. There is an added requirement for an 'Enable' signal in this case, but if it's absolutely necessary to keep the output low during power-on, then this is the only solution I know of.

    The circuit I would recommend:

    The pull-down resistor values can be very large (ex: 100k). They are there to keep the lines low during startup only.