SN74LVCR2245A: Current backflow function issue

user4263714

Part Number: SN74LVCR2245A
Other Parts Discussed in Thread: SN74LVCR2245

SN74LVCR2245A used as a buffer in my circuit, Signal defined form B to A, DIR pin and OE pin tied to GND

Power Pin tie to VCC3V3_A power rail

system power up, SN74LVCR2245A Port A side signal power up first, current backflow function is OK, partial-power-down is OK. VCC3V3_A is 0 V, when system open VCC3V3_A power rail, SN74LVCR2245A Port A side and controller power up, signal form Port B to Port A is OK

But ! when system close VCC3V3_A power rail,SN74LVCR2245A Port B side and the controller power off, I test VCC3V3_A Voltage is about 1V voltage in the power pin,

So,why do the partial-power-down do not function? is this current backflow from A side to B side?

over 5 years ago

0 user4263714 over 5 years ago

Prodigy 120 points

pic update below

0 Dylan Hubbard over 5 years ago in reply to user4263714

TI__Mastermind 42600 points

Hi,

When the device isn't powered the I/O pins go into a high-impedance state due to the Ioff circuitry. There is some leakage current during this state which is spec'd in the datasheet at +/- 10 uA. This could be what is causing the voltage you are measuring since the pins connected to the B side are left floating due to the high- impedance state of both the B inputs of the SN74LVCR2245A and the I/Os of the controller.

0 user4263714 over 5 years ago in reply to Dylan Hubbard

Prodigy 120 points

I forget a details ,that in B side ,a pull up resister is in the circuit as show in the picture as shown

0 user4263714 over 5 years ago in reply to Dylan Hubbard

Prodigy 120 points

There are some discribe mistakes, I need to correct it:

VCC3V3 is always power on

Before the FPGA turn on MOSFET,the VCC3V3_A is 0V

FPGA turn on MOSFET,A side work well,

When the B side FPGA turn off MOSFET , A side circuit was power off, and i test on A side power rail :VCC3V3_A ,it was 1V,

I resolved the issue to use OD buffer between SN74LVCR2245: A1 and FPGA, before PU resister

my question is ,why when A side power off, partical-power-down function seems invalid

0 Dylan Hubbard over 5 years ago in reply to user4263714

TI__Mastermind 42600 points

Hi,

I'm not sure if we can isolate the issue to the partial-power-down not working just yet. The FET you are using, is it a nMOS? Also what is your FPGA being powered by? Is the FPGA actually capable of driving the gate of that MOSFET?

Also this is a recommendation: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor.

0 user4263714 over 5 years ago in reply to Dylan Hubbard

Prodigy 120 points

The FET is nMOS, and my FPGAs is power by the VCC3V3 power tail, FPGA is able to driving the Gate of the nMOS, the FET is fullly turn-on

0 Dylan Hubbard over 5 years ago in reply to user4263714

TI__Mastermind 42600 points

The drain is connected to the VCC3V3?

0 user4263714 over 5 years ago in reply to Dylan Hubbard

Prodigy 120 points

The drain is connected to the VCC3V3!

0 Dylan Hubbard over 5 years ago in reply to user4263714

TI__Mastermind 42600 points

Okay thank you, that wasn't clear. If you are correctly driving the FET on and off then I think a good solution to this issue is to have a pull down on the VCC3V3_A node so the pin isn't just floating as soon as the switch opens.

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SN74LVCR2245A: Current backflow function issue