Dear all,
my AA is using the SN74LVT125 in the following condition:
Vcc 3.3V
Vin (1A,2A,3A,4A) = GND
1OEn, 2OEn, 3OEn, 4OEn driven by FPGA (GND, 3.3V levels)
Output 1Y, 2Y, 3Y, 4Y connected all together to Pull up resistor to 5V
The customer has noticed that output does not reach the Hi-Z stage (changing the status of OEn) unless a min current flows in the load (pull-up resistors).
With 14Kohm pull-up the xY reaches 1.4V when in Hi-Z, with 13Kohm pull-up the device works.
Is this phenomena correct ? Can you please give an explanation ?
regards,
Domenico