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SN74LVT125: Hi-Z mode doesn't work

Part Number: SN74LVT125

Dear all,

my AA is using the SN74LVT125 in the following condition:

Vcc 3.3V

Vin (1A,2A,3A,4A) = GND

1OEn, 2OEn, 3OEn, 4OEn driven by FPGA (GND, 3.3V levels)

Output 1Y, 2Y, 3Y, 4Y connected all together to Pull up resistor to 5V

The customer has noticed that output does not reach the Hi-Z stage (changing the status of OEn) unless  a min current flows in the load (pull-up resistors).

With 14Kohm pull-up the xY reaches 1.4V when in Hi-Z, with 13Kohm pull-up the device works.

Is this phenomena correct ? Can you please give an explanation ?

regards,

Domenico

  • Hello domenyko,
    It sounds like there is some confusion on what "Hi-Z" means. That's a high impedance, aka disconnected, output. If the output is placed in the "Hi-Z" state, then it is floating and the voltage at the node is unknown.
  • Hi Emrys,

    The output of the device are connected to 5V through a pull-up resistance. So when the Hi-Z is enabled through the OEn pin the output should go to 5V.

    The customer has noticed that it happens only if the pull-up is lower than 13kohm (to 5V).

    It seems that with resistances higher than 13kohm the output circuit of the buffer is not well biased when OEn drives it in Hi-Z.

    Is there any min sink current that needs to be allowed flowing in the output stage when it is in Hi-Z ?

    Regards,

    Domenico

  • Hi Domenico,
    Is it possible for you to post a schematic and scope shots of the input/output of the device?

    Also, has the device been swapped with a new IC to see if the issue goes away, or does this occur 100% of the time on all boards?
  • Hi Emrys,

    the customer has tested also other parts and has done a bench to test it.

    I've the schematic and the screenshots, but I prefer to share it by email.

    regards,

    Domenico

  • Thanks for Domenico,
    please mark this thread as "resolved" so we can close the issue.