SN74AUP1G74: D FLIP-FLOP question

Hello Daniel,

1. The pin6 is /CLR function. If we want to clear D-latch data, how long need /CLR be keep low?

The pulse duration is defined in the "Timing Requirements" table on the datasheet. The easy answer is "at least 5 ns"

2. Does the D latch work on CLK low to high only (rising edge) or both (rising and falling edge)?

This device is positive edge triggered (aka rising edge triggered).  The functional table for the device is in section 8.4.