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SN74V263: Replacement for Cypress CY7C4255V

Part Number: SN74V263

We are looking to replace the Cypress CY7C4255V with the SN74V263.  One issue that has come up is the retransmit pulse in standard mode. Fig 11 of data sheet shows that you need to wait until EF goes high before bringing REN low. Our current firmware does not use the EF signal but instead counts RCLK cycles. What is the maximum time for EF to return high after RT goes high?

We would also like some assistance in mapping the SN74V263 pins to the CY7C4255V functions as the TI part has many more features. Is there a TI resource to help?

Thanks,

Tom

  • Tom,
    Unfortunately the maximum time for EF to return high is not a spec'd parameter.
    This is a fairly old device, and it is not likely that the simulation models are still available to determine this from simulation.
    I would expect this to be short. It appears that it transitions high after the next rising edge of RCLK after valid setup time on RT to RCLK on the prior cycle.

    Regards,
    Wade
  • Thanks Wade. I see there is a zero latency retransmit feature which should be okay. In our design we keep RT low for an extended period of time with REN high. We then take RT high and wait for 3 RCLK cycles and then take REN low to begin reading. It sounds like either mode will work, but I hate to create a design for the standard retransmit not knowing the timing. 

    Regards,

    Tom