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SN74AVC16T245: Signal Integrity issues with SN74AVC16T245 level translator

Paul Buijsman
Prodigy 200 points
Part Number: SN74AVC16T245

We want to use TI SN74AVC16T245DGVR to translate DAC CLK and DATA[13:0] from 1.8V (FPGA I/O) to 3.3V (DAC I/O).

DAC_CLK = 125MHz (tCLK = 8ns).

Schematics:

Layout:

 

3V3 DAC CLK and DATA[13:0] traces are all on PCB bottom, and routed with 50 Ohm impedance.

Trace lengths are matched and only ~7.0mm long.

 

SI-analysis was performed on all signals using HyperLynx.

TI SN74AVC16T245DGVR IBIS file is downloaded from http://www.ti.com/lit/mo/scem451/scem451.ibs

Analog Devices AD9707 IBIS file is downloaded from https://www.analog.com/media/en/simulation-models/ibis-models/ad9707.ibs

 

1.8V signals are fine.

3.3V signals from level-shifter to DAC all look very bad:

 

The 100 Ohm series resistor that is mentioned as a possible solution is not an option, since there is not enough space on this fully populated PCB.

Besides, risetime and fall time of the signals are very asymmetrical. This makes it more difficult to get proper setup and hold times at the DAC device.

 

As an alternative a compatible level-shifter from NXP/Nexperia was used in the SI-analysis (74AVC16T245DGV).

https://assets.nexperia.com/documents/ibis-model/avc16t245.ibs

Those results looked very fine, with no excessive ringing and symmetrical edges.

 

from TI IBIS file: t_fall = ~3*t_rise

[Ramp]                      

| AVC16T245_IO_33

| variable           typ               min               max

dV/dt_r        1.97/2.35E-10     1.79/3.59E-10     2.16/1.73E-10

dV/dt_f         1.95/7.46E-10     1.78/1.00E-09     2.14/3.31E-10

 

from NXP IBIS file: t_fall = ~t_rise

[Ramp]

| AVC16T245_BION_33

| variable       typ                 min                 max

dV/dt_r 1.8726E+00/4.0904E-10 1.6970E+00/5.1595E-10 2.0455E+00/3.8291E-10

dV/dt_f 1.8731E+00/4.1216E-10 1.6981E+00/4.1634E-10 2.0457E+00/4.2922E-10

 

 Can you explain what goes wrong with the TI part?

Regards,

Paul

  • 0
    TI__Guru* 96591 points
    Hello and thanks for your post! Today is a holiday in the US. I just wanted to let you know that we will get back to you on Monday, November 26.
  • 0 in reply to Emrys Maier
    TI__Mastermind 42600 points
    Hi Paul,

    There might be an issue with the IBIS, I don't see any clear reasons for that ringing. If you can try out this model:

    www.ti.com/.../getliterature.tsp

    Its for the 8 channel version, but the output drivers should operate the same way. I'll work on it from my end as well, and if needed I can test on bench.
  • 0 in reply to Dylan Hubbard
    Prodigy 200 points

    Thank you Dylan,

    I have forwarded this info to the engineer who does the SI simulations for me. I'll get back to you as soon as there are some results.

    By the way, the ringing was only part of the issue that we saw. I was also not very happy with the large difference between t_rise and t_fall, as this makes timing closure more difficult. At first glance (looking at IBS-file with txt editor) t_rise and t_fall of the 8-ch version look similar to the 16-ch part. Can you confirm that in real life these edges are indeed very asymmetrical? FYI, we use 3V3 output.

    Kind regards,

    Paul

  • 0 in reply to Paul Buijsman
    Prodigy 200 points

    Hi Dylan,

    My SI engineer did a quick check. Unfortunately, the results of the 8ch-part (see below in red) look very similar to the 16-ch part (blue).

    If this is the real behavior of the part (both the ringing and very asymmetrical edges), then I'm afraid we can't use it and have to go to the NXP alternative.

    Can you somehow quickly bench-test this?

    Best regards,

    Paul

  • 0 in reply to Paul Buijsman
    TI__Mastermind 42600 points
    Hi Paul,

    I'd be glad to test this on the bench and get you data tomorrow. As for the difference for the rise/fall variation, this is due to the slight difference in drive strength of the high side and low side driver. I'm also in process of obtaining a different simulation software to rule out any issues with the hyperlynx software just as a sanity check.
  • 0 in reply to Dylan Hubbard
    TI__Mastermind 42600 points

    Hi Paul,

    The error is with the IBIS model itself so I will put a request in to put this on the queue for the modeling team to fix.

    As for my bench test the data is shown below. I matched your setup, with one caveat: my cables connecting my board to the oscope loaded the device with roughly 70 pF which you can see makes the edges rounded. Obviously, in your case I'd expect to see half that capacitance on the load so your waveform will be much more square.

  • 0 in reply to Dylan Hubbard
    Prodigy 200 points
    Hi Dylan,
    Thanks for doing the bench test.
    Indeed, there is no visible ringing. I'm still not 100% convinced that this is real component behavior, or that it is due to the capacitive load that is much larger than in our situation.
    The expected asymmetrical edges are not really visible, maybe also due to the capacitive load? Or is the IBIS model also incorrect in that aspect?

    Is it possible for you to repeat the bench test with an active probe, so that capacitive load is minimized?

    Best regards,
    Paul
  • 0 in reply to Paul Buijsman
    TI__Mastermind 42600 points

    Hi Paul,

    I made some modifications to the board Friday to allow me to reduce the capacitance. I'll have more data for you today. 

    I don't expect there to be a drastic difference between the rise and fall time as the output drivers are pretty well balanced.

  • 0 in reply to Dylan Hubbard
    TI__Mastermind 42600 points

    Hi Paul,

    Here are the new waveforms:

    I zoomed in and added a rise and fall time measurement so you can see how balanced the output driver is:

  • 0 in reply to Dylan Hubbard
    Prodigy 200 points

    Hi Dylan,

    Thanks for re-doing the test.

    These signals look good. No hint of ringing, and the edges are nice and symmetrical. 

    My conclusion is that the original IBIS-file was not OK on both these aspects. Do you know if and when an update of the IBIS-file can be expected? We would like to have this update for future use in other projects.

    Best regards,

    Paul