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Original question:

[FAQ] What does 'partial power down' or 'Ioff' mean in the datasheet?

AND Gate Output State During Power-Up

Peiheng Liu
Prodigy 620 points
Other Parts Discussed in Thread: SN74HC573A-Q1, SN74LVC2G08-Q1

Hi,

I just went through these 2 threads from our forum and there are very helpful! Great thanks to Emrys!

https://e2e.ti.com/support/logic/f/151/p/731172/2698649

https://e2e.ti.com/support/logic/f/151/t/755848

Here I have one more doubt to clear. In automotive safety critical application. Latches like SN74HC573A-Q1 could ensure a defined state during power-up by tying the OE/ to Vcc and pull down at Q, but is the Q output glitch free during power up? Would this also applies to SN74LVC2G08-Q1, with pull down resistors to on both A/B/Y?

Great thanks for your help! 

  • 0
    TI__Guru* 96591 points

    Hi Peiheng,

    I'm glad you're finding the information on the forums helpful. I always strive to provide a complete answer just so that people will find these threads useful in the future.

    I should point out two lines in the SN74HC573A-Q1 datasheet to answer your question:

    (1) To ensure the high-impedance state during power up or power down, OE\ should be tied to Vcc through a pullup resistor...

    (2) OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

    From (1) above, if OE\ is held HIGH (equal to Vcc) while the supply is being ramped, the outputs will remain in a high impedance state -- which means that your pull-down resistors will keep the outputs LOW during startup without any glitches.

    From (2) above, doing this will not affect the startup state of the internal latches. They will still have a random state and when the device in enabled, the outputs will change depending on the latch states. This can easily be fixed by clocking data through the latch prior to enabling the outputs -- but it's something important to know about.

    As for the SN74LVC2G08-Q1, this device doesn't have an output enable. It will begin driving the line as soon as the supply is large enough to bias all the internals (likely about 1V). Holding the inputs at ~0V will ensure that the SN74LVC2G08-Q1 'sees' LOW inputs and the AND function will produce a LOW output once the correct bias is available. You might see a slight rise in output voltage before the device turns on, but this is usually on the order of ~50mV.