SN74LVC1G74: Need truth table data when CLR=H, PRE=H and CLK =H??

Sagar Kumar18

Part Number: SN74LVC1G74
Other Parts Discussed in Thread: TPS3422

I am using TPS3422+SN74LVC1G74 in Latched reset signal solution attached the image of circuit. When my device got power up, first PRE gone High then after some delay(by RC circuit) CLR gone high and CLK already is in High state due to pull up on TPS3422 O/p RST pin. Please let me know at this particular condition what will be the behavior of Q, since truth table(Attaching truth table) does not show this condition.

Condition is CLR= ''H'', PRE= ''H'' CLK= ''H''

over 5 years ago

0 Emrys Maier over 5 years ago

TI__Guru* 96591 points

Hi Sagar,
The clock of this device is edge triggered -- ie it will not change anything if it not a rising edge. This is indicated by the up arrows in the function table.

If you have cleared the device, then Q = L and Q\ = H.

If this resolves your question, please click the green "this resolved my issue" button. if not, please respond and I will continue to help.

0 Sagar Kumar18 over 5 years ago in reply to Emrys Maier

Prodigy 180 points

Hi Maier

Its means on this condition CLR= ''H'', PRE= ''H'' CLK= ''H'', Q will contain previous state. is my understanding correct?

0 Emrys Maier over 5 years ago in reply to Sagar Kumar18

TI__Guru* 96591 points

Hi Sagar,
Yes, that's how an edge-triggered flip-flop works.

Logic

Logic forum

SN74LVC1G74: Need truth table data when CLR=H, PRE=H and CLK =H??