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SN74AXC4T774: BUS contention

Rongpeng Zhai
Prodigy 230 points
Part Number: SN74AXC4T774
Other Parts Discussed in Thread: TXB0104

Hi, 

I have a question for the bidirectional Level translator SN74AXC4T774 when there is a bus contention:

The connection is shown as below:

FPGA --- SN74AXC4T774--- Unknown DUT

SN74AXC4T774 Setting: Direction from FPGA to DUT.

FPGA set: output data =0.

DUT set: output date =1. (for 3.3V)

As a result, the level translator's output will be pulled down. The 3.3V from DUT will be shorted to GND.

As I know about the SN74AXC4T774, there is a idea to add a series resistor of 150 ohm to limit the current below 25mA, it is safe for AXC device.

For normal operation, the drive strength of the FPGA is 12mA, also for the DUT. This is OK.

But, there is a worst case, the DUT is unknown for different products. A broken DUT can be short to 3.3V power supply. Therefore, the 150 ohm is useful to limit the current.

However, this IO is used for high bandwidth >50MHz. Thus, the RC is important. With 150ohm and 20pF, the cut frequency is 53MHz. The capacitance in the circuit is >50pF.

It is not preferred to add a resistor in this chain.

Do you have any idea to protect the bus contention without the series resistors?

Thanks.

  • 0
    Guru 244220 points

    The TXB0104 has very low DC drive strength, but 100 Mbps is its upper limit with 15 pF; it probably cannot handle that capacitance.

    I guess the capacitance comes from some kind of socket and cannot be reduced?

  • 0 in reply to Clemens Ladisch
    Prodigy 230 points

    Hi Clemens,

    I make a mistake here:

    FPGA ---- SN74AXC4T774 --- Analog switch ---- Unknown DUT.

    The capacitance of the analog switch is 47pF max.

    When we drive from FPGA to the connected DUT, we required enough drive strength 12mA.

    That's why TXB, LSF passive level translator is not selected.

    The drive strength of SN74AXC4T774 is OK for 12mA.

    And the problem is not caused by the level translator. It's depend on the DUT.

    We considered when DUT is short to 3.3V power supply, and the level translator is pull down to GND.

    The drive strength of the level translator is not important here.

  • 0 in reply to Clemens Ladisch
    Prodigy 230 points

    SN74AXC4T774:

    Io Continuous output current: -50mA to 50mA.

        Continuous current through VCC or GND: -100mA to 100mA.

    What is the correct current limit, when a bus contention is there drive one output for different voltage?

  • 0 in reply to Rongpeng Zhai
    Guru 244220 points

    When you have bus contention on all four lines in the same direction, you have to limit the overall current to 100 mA, so at most 25 mA per channel.

    If you can ensure that you do not have contention on all four channels, you can use a higher limit (in the best case, up to 50 mA per channel, corresponding to 66 Ω).

    Furthermore, the FPGA's and the DUT's drivers also have an output impedance, which you can subtract from the current-limiting resistor. For example, if the FPGA and DUT have a typical VOL of 0.2 V for 12 mA, their output impedance is 0.2 V / 12 mA ≈ 16.7 Ω, and the current-limiting resistor can be 66 Ω − 16.7 Ω − 16.7 Ω ≈ 33 Ω.