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  • TI Thinks Resolved

SN74LV165A: If SER is not pull down, will it influence output data?

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Part Number: SN74LV165A

if SER is not pull down, will it influence output data?

  • The datasheet says:

    The parallel inputs to the register are enabled while SH/LD is held low, independently of the levels of CLK, CLK INH, or SER.

    So it does not matter whether SER is low or high. However, it is necessary for SER to have a valid logic level; see footnote (1) in section 6.3:

    All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the Implications of Slow or Floating CMOS Inputs application report.

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