• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 18 subscribers
  • Views 272 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN74AVC2T244: Rise and fall times

Dennis McGlumphy
Expert 1390 points
Part Number: SN74AVC2T244
Other Parts Discussed in Thread: SN65MLVD203, 2N7001T, , SN74AXC2T45

SN74AVC2T244Dear Sirs

I'm interfacing a 1.8v output FPGA to a 3.3V MLVDS system that will be running at 100MHz.  I plan to have the 1.8V FPGA output feed into a SN74AVC2T244 or 2N7001T and then into a SN65MLVD203.  The receiver will be a MLVDS compatible FPGA.  The data sheets of these parts states the bit rates are 100Mbps and greater.  My question is, what is the rise and fall times of these parts?  Any other solutions for this issue are welcome.  Thank you for your time.   

  • 0
    TI__Guru 55970 points

    Hi Dennis,

    SN74AVC2T244 is dual channel unidirectional device while 2N7001T is single channel. Are you planning on using 2 of them? Since the operating frequency is 100Mhz( 200Mbps) I would suggest considering the SN74AXC2T45 device( 2 channel) to support this high frequency as noted in the datasheet features ( up to 380Mbps).

    The rise and fall times are dependent on the cap loading, and interfacing with a high impedance input generally means that the rise/fall times will be <5-7ns. 

    The common risks of discrete voltage translation app note (http://www.ti.com/lit/an/scea062a/scea062a.pdf) has a simulation of the 2N7001T with 2.2ns rise time for 3.3V translation. The SN74AXC2T45 will be similar as it has the same output current drive as 2N7001T.

  • 0 in reply to ShreyasRao
    Expert 1390 points

    Thank you for the quick response.  Insofar as the capacitive loading is concerned, the FPGA receivers and transmitters are suppose to adhere to the TIA/EIA-899 (electrical characteristics of multipoint-low-voltage differential signaling (MLVDS)) standard.  This is approximately 2.5pF differential and 3pF common mode.  What is your guess for the rise and fall times for this loading?  The SN74AXC2T45 is a nice part, but my bus will be full duplex and therefore I have no need for direction changing. 

    Q. SN74AVC2T244 is dual channel unidirectional device while 2N7001T is single channel. Are you planning on using 2 of them?

    A. Because of the topology of the PCB layout, I will be using both the SN74AVC2T244 and 2N7001T. 

  • 0 in reply to Dennis McGlumphy
    TI__Guru 55970 points

    hi Dennis,

    With such low loading, the rise and fall times would typically not exceed 5ns

  • 0 in reply to ShreyasRao
    Expert 1390 points

    Sorry about this, I forgot to say this is a backplane design that could have as many as 32 slots (32 MLVDS loads).

  • 0 in reply to Dennis McGlumphy
    TI__Guru 55970 points

    Do you mean one output channel( 2N7001T / AVC2T) driving 32 loads of 3pF each? so about 100pF total loading?

    In that case, the rise time could be ~8-12ns. You can evaluate the timing using the IBIS model of the 2N7001T or the AVC.

    I calculate this by the RC loading.

    R = (Vcc-Voh) / Ioh

    = ~33ohm

    3RC = ~10ns rise time.

    Usually, it will be lower than that.