SN74LVTH245A: SNLVTH245A clock duty cycle issue

What is the supply voltage? Is the input signal a rail-to-rail square wave, or some other waveform?

(The bus-hold circuit of the SN74LVTH245A requires a certain input current, and if the input signal is not symmetric around the switching threshold, this is likely to introduce pulse width distortion.)

The supply power is 3.3V. Input signal is as below.

Input signal:

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How exactly did you measure the duty cycle of that?

Am I correct in observing that this signal never reaches 0 V?

You best bet would probably be a Schmitt-trigger buffer such as the SN74LVC1G17, either instead or in front of the SN74LVTH245A.

How exactly did you measure the duty cycle of that?

=> I measure tthe clock by active probe with short GND cable.

Am I correct in observing that this signal never reaches 0 V?

=> Yes. The clock has a DC offset.

Could you suggest me the logic IC for below clock design ? Thanks.

125MHz_clock -> buffer (logic IC?) -> 3.3V to 1.8V (logic IC?) -> DUT

The input clock is not a proper logic signal, so a plain logic IC will not really help. I'd suggest the following circuit, which generates the switching threshold as the average of the input signal:

Try something like R = 10 kΩ, C = 47 pF, comparator = DS90LV012A.

To convert the output signal from 3.3 V to 1.8 V, you can use any logic buffer with an overvoltage-tolerant input (e.g., SN74LVC1G34) running at V_CC = 1.8 V.