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Part Number: SN74LVC1G175
I am using D-Type Flip Flop SN74LVC1G175. Pin 3 has 5 Volts on it, pin 2 is connected to ground, and pins 1, 5 and 6 are OFF. Why does pin 4 register ON?
What does "OFF" mean, 0 V or open? In the latter case, the charge on the decoupling capacitor might be enough to power the device.
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In reply to Clemens Ladisch:
I mean there is no external Voltage applied to VCC. It's 0 Volts. You mention a decoupling capacitor. Is there somewhere I can get a detailed schematic?
In reply to Kyle Smith1:
"0 V" and "no external voltage" are two different things. When you simply disconnect the supply, VCC does not necessarily go immediately to 0 V.
All CMOS logic devices require a low-impedance power supply, which usually implies a capacitor near the device.
Please show a schematic of your circuit, or an image of your board.
I suppose I have a lot to learn, then.
See the schematic and Voltage data below. The chip is powered from a 5V rail, and the rail Voltage is zero. However, further tests have showed that there is a short CLK Voltage rise that coincides with the latching of D to Q, but it is arrested back to zero before the rise at D finishes. That might be an issue with something upstream of the CLK pin.
Is there a charge stored internal to this chip that would make a Voltage rise at Q with zero Volts externally applied to VCC?
There will be no influence at the input from the voltage changing on Vcc. This may be something down stream connected to Clk that may also be powering down.
Check out our new AXC family of Voltage Translators!
Watch the Introduction to AXC Family to find out more about the family.
In reply to Dylan Hubbard:
So, to be clear, you're saying that this device will NOT latch D to Q, if there is never a Voltage applied to VCC?
If the supply is 0 V then the Ioff circuitry disables the output otherwise there is no guarantee that a rising signal on the clk pin will trigger the device.
Thank you. I'll start looking elsewhere for the source of my anomalous Voltage.
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