Hi Ronald-san,
Thank you for your reply.
The SN74LVC1G34 rise speed specification is for Vcc.
Can this rule apply to the CLR pin of SN74LVC123?
I think that the input of CLR pin is a normal CMOS input, if the input signal is noisy, it will affect the operation.
In this case, The input signal of CLR is not noisy.
I also think the Q output operates fine if the threshold of the CLR pin is exceeded.
Could you explain why this is the phenomenon?
Best regards,
Yuto Sakai