Part Number: TXB0108
Hi,We are using a TXB0108 translator to translate 1V2 xczu3eg FPGA bank push-pull logic to 3V3 push-pull logic on MT9V032 sensor. If we use the TXB, it damages the FPGA irrecoverably on first turn on. During turn on the FPGA is High-Z. If a TXS0108 translator is used, this behavior is not observed.The board in question is Ultra96-V2What could be causing the issue?
Does this always happen, with every I/O pin? Or is the entire FPGA broken?
I'd like to see oscilloscope traces of what happens during turn on.
The most likely reason would be overvoltage, but the TXB should never output a voltage above 1.2 V. Are the FPGA bank and the TXB powered by the same supply?
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In reply to Clemens Ladisch:
We are using an Ultra 96 V2 devboard and the pins themselves seem to function normally after the board/fpga is damaged. However, we are using internal deserialiser and impedance matching (DCI) resources (for LVDS signal) which seem to cease functioning completely after using TXB. These resources are not even connected to the TXB's I/O pins.
As for the traces, the 1.2V side and 3.3V just ramps up steadily on the VccA and VccB pins, see pdf attached. If I/O pins are tested, the same result is observed. The bank and TXB are not powered by the same supply. The FPGA bank I/Os have their own power supply and the TXB is powered by an LDO.
In reply to Paulius Klimenko:
When powering up, the TXB can output a 1.2 V signal at all A pins. Is it possible that this happens before the FPGA bank has powered up, and that the FPGA does not allow voltages higher than its own supply?
The TXB 1.2V is provided by an LDO, which is powered by a PMIC with a 5V DC/DC on the Ultra96 board. Same PMIC also powers the 1V2 FPGA bank with 1V2 DC/DC. Since the behavior you described happens with TXS0108 as well, I doubt it would be causing the problem with the damaged FPGA as the TXS works perfectly.
I would expect a linear regulator to power up faster than a switching supply.
The TXB and TXS have different architectures, so it would be plausible that the TXB drives the I/O high earlier.
Can you keep the EN pin of the TXB low for a certain time while powering up?
You're probably right about the start times. However, the part that is damaged inside the FPGA is not even connected to the TXB pins. We can try keeping the pin low, but we are burning quite expensive boards and buying another one just for a test is not feasible for us.
We will probably control the EN of the TXS shifter in the future as it did not damage anything even when EN was not controlled.
I suspect that the high voltage from the TXB goes through the ESD diodes into the FPGA's 1.2 V power supply, and thus affects anything connected to that supply.
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