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SN74LVC1G80: How does a slow transitioning clock input affect the device?

Other Parts Discussed in Thread: SN74LVC1G80

Thanks!

By the way, when I test the SN74LVC1G80,when CLK is high and D is low ,the output is high. If CLK rises slowly, whether the output will still be high?Or will output Q0, and then output high?

  • Hello,

    I split this into a new thread since this is a separate topic. We keep topics separated to help anyone who find this through a search engine in the future to avoid confusion.

    I was hoping that the system would bring along Clemens's response, but it seems that it didn't, so I'll quote him here:

    Clemens Ladisch said:

    The output changes when the device detects a rising edge on the CLK input, i.e., when the voltage at the CLK pin crosses the switching threshold.

    It is not allowed for CLK to rise slowly; see the Δt/Δv limit in the recommended operating condiions.