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SN74LVC1G123: Glitch-Free Power-Up Reset on Outputs

Mark Hartter
Prodigy 110 points
Part Number: SN74LVC1G123

The datasheet mentions "Glitch-Free Power-Up Reset on Outputs", but I'm not finding a definition for this. 

Our design holds !A low.  B, !CLR, and VCC all come up together.  We're seeing inconsistent behavior at power-up (sometime see an output pulse generated, sometimes not) that I suspect is due to timing around this "glitch free power-up".

Thanks!

  • 0
    TI__Guru* 96591 points

    Hi Mark,

    There's an internal power-on reset circuit that disables the device for a short time at startup to prevent spurious outputs. The device was tested with a minimum ramp rate of 1 V/ms.

    Can you share a scope shot of the two inputs plus the timing capacitor and output?

  • 0 in reply to Emrys Maier
    Prodigy 110 points

    Hi Emrys,

    Thanks for the info.  So does that mean:

    If I ramp power (Vcc) at 1 V/ms (or faster), then any A!, B, CLR! transitions up until t = X after Vcc = 1.65V (min operating voltage) are ignored?

    If this is accurate, can you provide a time for "X" above?

    Thanks,

    Mark

  • 0 in reply to Mark Hartter
    TI__Guru* 96591 points

    Hey Mark,

    Yes, that is accurate. The POR circuit directly forces the internal latches to their startup states, bypassing the inputs.

    Under typical conditions, we'd expect to see the power on reset circuit remain active for 2 to 3 ms. At cold temps this gets longer, up to about 16ms at -40C.

    In the absolute worst case, with 'weak material' and at -40C we could see up to ~160ms of delay before the device will start working. I doubt that we would ever actually produce a device like this, but that should give you  really solid maximum boundary to avoid.

  • 0 in reply to Emrys Maier
    Prodigy 110 points

    Thanks Emrys!  Appreciate your support.