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SN74LVC1G123: False Output at start up

Part Number: SN74LVC1G123

Dear Specialists,

My customer is evaluating SN74LVC123 and encountering a problem.

I would be grateful if you could advise.

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In SN74LVC1G123DCUR, one pulse signal of about 80ms is output from output terminal Q at 0.93V 

on the way from Vcc = 0V to 5V.

 (In the system, the circuit in the subsequent stage will operate due to the influence of the output signal.)

 (1)Could you please let us know the cause of the phenomenon.

 (2)We'd like to know how the risig and falling edge of the A, B and CLR determined.

Could you please see the waveform and schematic.

Question about SN74LVC1G123DCUR.xlsx

According to the Function Table, a pulse may be output when the IC_B or CLR transitions from L to H.

However, 0.93V is out of the operating rating.

We are looking forward to waiting your advice.

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I appreciate your great help in advance.

Best regards,

Shinichi

  • Hi Shinichi,

    Thanks for the details you provided. This device should have a clear circuit to keep the output from powering up High. Can you test without the output load? Also can you add a scope channel to the Rext/Cext pin?

    What is happening to the A input? I don't see what its all connected, but what I can see is an RC circuit connected between it and Vcc so I wouldn't expect it to track the supply like it does.

  • Hi Dylan,

    Thank you for your reply.

    I'll confirm with the customer about your comment.

    When I get information, I'll feedback to you.

    I appreciate your great help and cooperation.

    Best regards,

    Shinichi

  • Hi Dylan,

    I could obtain the waveform and schematic.

    CH2(Orange):Vcc、IC_B, IC_CLR

    CH3(Green):IC_Q

    CH5(Red):IC_A

    CH8(Purple):Rext/Cext

    A comparator is connected to IC_A.

    Could you please see attached excel file.

    additional waveform and schematic of SN74LVC1G123DCUR.xlsx

    ---

    The waveform and connection from the customer, I assumed the following scenario.

    The voltage rises at start up.

    And then The output of the comparator becomes 0V.

    After Vcc, IC_B and IC_CLR reach 770mV, the Rext / Cext voltage begins to drop.

    IC_Q begins to increase.

    In other words, it seems that IC_A is L, IC_B is L to H, and IC_CLR is H.

    And although the voltage is low, the device is outputting a pulse.

    Are these correct?

    Also, could you please let me know the measures.

    Should I keep the CLR L, A H, or B L at startup?

    Also, in this case, if A is not set to L, the pulse will not be output.

    ---

    I appreciate your great help and cooperation

    Best regards,

    Shinichi

  • Hello Shinichi-san,

    It looks like B and CLR are tracking the supply which should make it so that there is no transition at Q based on this inputs.

    It looks like A is having a high to low transition in the period you highlight, which may be causing the Q output to respond and then be high until the Rext/Cext reaches the threshold value at which point the pulse ends.

    Is it possible to make sure that the A input tracks the supply as well?

    If the A input tracks the A supply then it may not cause this Q output to trigger on startup.

    Best,

    Michael

  • Hi Michael,

    Thank you for your reply.

    I understand that there is a possibility of malfunction because the A input became L at startup.

    I'll share this information with the customer.

    I appreciate your great help and cooperation.

    Best regards,

    Shinichi

  • Shinichi-san,

    Happy to help, let us know what more you find and we will be happy to review and help.

    Michael

  • Hi Michael,

    Thank you for your reply.

    I contacted the customer, I'm still waiting for the response.

    But I think the customer understands your suggestion.

    If they have additional question, I consult you again.

    I appreciate your great help and cooperation.

    Best regards,

    Shinichi