Buffer IC with drive strength of 50mA per channel

The logic family with the highest drive strength is LVC, but you would still need to combine multiple outputs.

Do you need to source or sink the current, or both? There are stronger buffers, but with open-drain outputs.

We need Source and sink both t drive strength of 50mA per channel. Can we get some 4 channel or 8channel IC for this requirement?

Can you suggest part numbers. The key challenge is Voltage range must be 1.2V to 5.5V.

Open drain option is not preferred. We would be using it for SPI.

There are no large ICs whose outputs go up to 5 V. You have to use multiple SN74LVC2G17 or SN74LVC3G17 devices, and combine at least two outputs to get 50 mA.

Ok, Can we connect 1.2V to VCC pin of these 2 ICs and can we connect 1.2V logic at the Input pins of these ICs?

So I have 2 questions :

1. Can we have 1.2V on SUPLLY pin and 1.2V IO level on IO pins for these ICs.

2. Shorting 2 channels will have any impact on datarate? Will it reduce at huge range?

Regards,

Vijetha

The minimum supply voltage of LVC is 1.65 V, and that reduces the possible current.

At 1.2 V, the strongest family is AUC, and that would provide 3 mA per output.

Why do you need 50 mA for SPI anyway? What is the actual problem you're trying to solve?

I am basically working on below requirement:

The SPI from a MCU at 3.3V level is to be translated to any voltage between 1.2V to 5.5Vthat would be connected to different types of sensors.

But we also need 20Mbps speed support or 50mA of drive strength on each SPI line. But both will not be needed simultaniously (meaning we need either 20Mbps at lower drive strength or Higher drive strength at lower data rate).

Currently the translator we are using can operate in the range of 1.2V to 5.5V but its drive strength is very low.

So we wanted to use a MUX here.

MUX Input 1 : Translator output : this will serve High datarate but low drive strength.

MUX INPUT 2 : Connect the translator output to a buffer and buffer output shall be connected to MUX INPUT 2. This will serve High drive strength but lower speed.

Whenever we need HIGH SPEED, we select MUX INPUT1 and whenever we need high drive strength of 50mA per channel we would use MUX INPUT2.

Hope you understood our requirement.

So here what I am checking with you is that buffer that is used at MUX INPUT2. Here all that I need is the support of 1.2V to 5.5V IO VOLTAGE + min 50mA of drive strength per channel.

Can you suggest me accurate part number for this requirement? 

Whether we have any IC that can give min 50mA per channel or whether shorting 2 channels for each signal is the only solution we have?

If we short the 2 channels, will it reduce the data rate further?

In general, devices with higher drive strength support higher speeds.

Combining several CMOS outputs is no problem; see [FAQ] Can I connect two outputs from a CMOS logic device together directly?

A good solution for 50 mA at 1.2 V does not really exist. What exactly do you need 50 mA for? What kind of load do you need to drive?